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CPU boot mode
[qemu/qemu_0_9_1_stable.git] / cpu-exec.c
blob8d91520408a422e54e8bee05307b226248b26130
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 void cpu_loop_exit(void)
44 {
45 /* NOTE: the register at this point must be saved by hand because
46 longjmp restore them */
47 regs_to_env();
48 longjmp(env->jmp_env, 1);
49 }
50
51 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
52 #define reg_T2
53 #endif
54
55 /* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
57 */
58 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 {
60 #if !defined(CONFIG_SOFTMMU)
61 struct ucontext *uc = puc;
62 #endif
63
64 env = env1;
65
66 /* XXX: restore cpu registers saved in host registers */
67
68 #if !defined(CONFIG_SOFTMMU)
69 if (puc) {
70 /* XXX: use siglongjmp ? */
71 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
72 }
73 #endif
74 longjmp(env->jmp_env, 1);
75 }
76
77
78 static TranslationBlock *tb_find_slow(target_ulong pc,
79 target_ulong cs_base,
80 uint64_t flags)
81 {
82 TranslationBlock *tb, **ptb1;
83 int code_gen_size;
84 unsigned int h;
85 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
86 uint8_t *tc_ptr;
87
88 spin_lock(&tb_lock);
89
90 tb_invalidated_flag = 0;
91
92 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93
94 /* find translated block using physical mappings */
95 phys_pc = get_phys_addr_code(env, pc);
96 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 phys_page2 = -1;
98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
104 if (tb->pc == pc &&
105 tb->page_addr[0] == phys_page1 &&
106 tb->cs_base == cs_base &&
107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
110 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 TARGET_PAGE_SIZE;
112 phys_page2 = get_phys_addr_code(env, virt_page2);
113 if (tb->page_addr[1] == phys_page2)
114 goto found;
115 } else {
116 goto found;
117 }
118 }
119 ptb1 = &tb->phys_hash_next;
120 }
121 not_found:
122 /* if no translated code available, then translate it now */
123 tb = tb_alloc(pc);
124 if (!tb) {
125 /* flush must be done */
126 tb_flush(env);
127 /* cannot fail at this point */
128 tb = tb_alloc(pc);
129 /* don't forget to invalidate previous TB info */
130 tb_invalidated_flag = 1;
131 }
132 tc_ptr = code_gen_ptr;
133 tb->tc_ptr = tc_ptr;
134 tb->cs_base = cs_base;
135 tb->flags = flags;
136 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
137 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138
139 /* check next page if needed */
140 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
143 phys_page2 = get_phys_addr_code(env, virt_page2);
144 }
145 tb_link_phys(tb, phys_pc, phys_page2);
146
147 found:
148 /* we add the TB in the virtual pc hash table */
149 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
150 spin_unlock(&tb_lock);
151 return tb;
152 }
153
154 static inline TranslationBlock *tb_find_fast(void)
155 {
156 TranslationBlock *tb;
157 target_ulong cs_base, pc;
158 uint64_t flags;
159
160 /* we record a subset of the CPU state. It will
161 always be the same before a given translated block
162 is executed. */
163 #if defined(TARGET_I386)
164 flags = env->hflags;
165 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
166 flags |= env->intercept;
167 cs_base = env->segs[R_CS].base;
168 pc = cs_base + env->eip;
169 #elif defined(TARGET_ARM)
170 flags = env->thumb | (env->vfp.vec_len << 1)
171 | (env->vfp.vec_stride << 4);
172 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
173 flags |= (1 << 6);
174 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
175 flags |= (1 << 7);
176 cs_base = 0;
177 pc = env->regs[15];
178 #elif defined(TARGET_SPARC)
179 #ifdef TARGET_SPARC64
180 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
181 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
182 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
183 #else
184 // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor
185 flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3)
186 | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
187 | env->psrs;
188 #endif
189 cs_base = env->npc;
190 pc = env->pc;
191 #elif defined(TARGET_PPC)
192 flags = env->hflags;
193 cs_base = 0;
194 pc = env->nip;
195 #elif defined(TARGET_MIPS)
196 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
197 cs_base = 0;
198 pc = env->PC[env->current_tc];
199 #elif defined(TARGET_M68K)
200 flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
201 | (env->sr & SR_S) /* Bit 13 */
202 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
203 cs_base = 0;
204 pc = env->pc;
205 #elif defined(TARGET_SH4)
206 flags = env->sr & (SR_MD | SR_RB);
207 cs_base = 0; /* XXXXX */
208 pc = env->pc;
209 #elif defined(TARGET_ALPHA)
210 flags = env->ps;
211 cs_base = 0;
212 pc = env->pc;
213 #else
214 #error unsupported CPU
215 #endif
216 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
217 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
218 tb->flags != flags, 0)) {
219 tb = tb_find_slow(pc, cs_base, flags);
220 /* Note: we do it here to avoid a gcc bug on Mac OS X when
221 doing it in tb_find_slow */
222 if (tb_invalidated_flag) {
223 /* as some TB could have been invalidated because
224 of memory exceptions while generating the code, we
225 must recompute the hash index here */
226 T0 = 0;
227 }
228 }
229 return tb;
230 }
231
232
233 /* main execution loop */
234
235 int cpu_exec(CPUState *env1)
236 {
237 #define DECLARE_HOST_REGS 1
238 #include "hostregs_helper.h"
239 #if defined(TARGET_SPARC)
240 #if defined(reg_REGWPTR)
241 uint32_t *saved_regwptr;
242 #endif
243 #endif
244 #if defined(__sparc__) && !defined(HOST_SOLARIS)
245 int saved_i7;
246 target_ulong tmp_T0;
247 #endif
248 int ret, interrupt_request;
249 void (*gen_func)(void);
250 TranslationBlock *tb;
251 uint8_t *tc_ptr;
252
253 if (cpu_halted(env1) == EXCP_HALTED)
254 return EXCP_HALTED;
255
256 cpu_single_env = env1;
257
258 /* first we save global registers */
259 #define SAVE_HOST_REGS 1
260 #include "hostregs_helper.h"
261 env = env1;
262 #if defined(__sparc__) && !defined(HOST_SOLARIS)
263 /* we also save i7 because longjmp may not restore it */
264 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
265 #endif
266
267 env_to_regs();
268 #if defined(TARGET_I386)
269 /* put eflags in CPU temporary format */
270 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
271 DF = 1 - (2 * ((env->eflags >> 10) & 1));
272 CC_OP = CC_OP_EFLAGS;
273 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
274 #elif defined(TARGET_SPARC)
275 #if defined(reg_REGWPTR)
276 saved_regwptr = REGWPTR;
277 #endif
278 #elif defined(TARGET_M68K)
279 env->cc_op = CC_OP_FLAGS;
280 env->cc_dest = env->sr & 0xf;
281 env->cc_x = (env->sr >> 4) & 1;
282 #elif defined(TARGET_ALPHA)
283 #elif defined(TARGET_ARM)
284 #elif defined(TARGET_PPC)
285 #elif defined(TARGET_MIPS)
286 #elif defined(TARGET_SH4)
287 /* XXXXX */
288 #else
289 #error unsupported target CPU
290 #endif
291 env->exception_index = -1;
292
293 /* prepare setjmp context for exception handling */
294 for(;;) {
295 if (setjmp(env->jmp_env) == 0) {
296 env->current_tb = NULL;
297 /* if an exception is pending, we execute it here */
298 if (env->exception_index >= 0) {
299 if (env->exception_index >= EXCP_INTERRUPT) {
300 /* exit request from the cpu execution loop */
301 ret = env->exception_index;
302 break;
303 } else if (env->user_mode_only) {
304 /* if user mode only, we simulate a fake exception
305 which will be handled outside the cpu execution
306 loop */
307 #if defined(TARGET_I386)
308 do_interrupt_user(env->exception_index,
309 env->exception_is_int,
310 env->error_code,
311 env->exception_next_eip);
312 #endif
313 ret = env->exception_index;
314 break;
315 } else {
316 #if defined(TARGET_I386)
317 /* simulate a real cpu exception. On i386, it can
318 trigger new exceptions, but we do not handle
319 double or triple faults yet. */
320 do_interrupt(env->exception_index,
321 env->exception_is_int,
322 env->error_code,
323 env->exception_next_eip, 0);
324 /* successfully delivered */
325 env->old_exception = -1;
326 #elif defined(TARGET_PPC)
327 do_interrupt(env);
328 #elif defined(TARGET_MIPS)
329 do_interrupt(env);
330 #elif defined(TARGET_SPARC)
331 do_interrupt(env->exception_index);
332 #elif defined(TARGET_ARM)
333 do_interrupt(env);
334 #elif defined(TARGET_SH4)
335 do_interrupt(env);
336 #elif defined(TARGET_ALPHA)
337 do_interrupt(env);
338 #elif defined(TARGET_M68K)
339 do_interrupt(0);
340 #endif
341 }
342 env->exception_index = -1;
343 }
344 #ifdef USE_KQEMU
345 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
346 int ret;
347 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
348 ret = kqemu_cpu_exec(env);
349 /* put eflags in CPU temporary format */
350 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
351 DF = 1 - (2 * ((env->eflags >> 10) & 1));
352 CC_OP = CC_OP_EFLAGS;
353 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
354 if (ret == 1) {
355 /* exception */
356 longjmp(env->jmp_env, 1);
357 } else if (ret == 2) {
358 /* softmmu execution needed */
359 } else {
360 if (env->interrupt_request != 0) {
361 /* hardware interrupt will be executed just after */
362 } else {
363 /* otherwise, we restart */
364 longjmp(env->jmp_env, 1);
365 }
366 }
367 }
368 #endif
369
370 T0 = 0; /* force lookup of first TB */
371 for(;;) {
372 #if defined(__sparc__) && !defined(HOST_SOLARIS)
373 /* g1 can be modified by some libc? functions */
374 tmp_T0 = T0;
375 #endif
376 interrupt_request = env->interrupt_request;
377 if (__builtin_expect(interrupt_request, 0)
378 #if defined(TARGET_I386)
379 && env->hflags & HF_GIF_MASK
380 #endif
381 ) {
382 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
383 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
384 env->exception_index = EXCP_DEBUG;
385 cpu_loop_exit();
386 }
387 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
388 defined(TARGET_PPC) || defined(TARGET_ALPHA)
389 if (interrupt_request & CPU_INTERRUPT_HALT) {
390 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
391 env->halted = 1;
392 env->exception_index = EXCP_HLT;
393 cpu_loop_exit();
394 }
395 #endif
396 #if defined(TARGET_I386)
397 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
398 !(env->hflags & HF_SMM_MASK)) {
399 svm_check_intercept(SVM_EXIT_SMI);
400 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
401 do_smm_enter();
402 #if defined(__sparc__) && !defined(HOST_SOLARIS)
403 tmp_T0 = 0;
404 #else
405 T0 = 0;
406 #endif
407 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
408 (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) &&
409 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
410 int intno;
411 svm_check_intercept(SVM_EXIT_INTR);
412 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
413 intno = cpu_get_pic_interrupt(env);
414 if (loglevel & CPU_LOG_TB_IN_ASM) {
415 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
416 }
417 do_interrupt(intno, 0, 0, 0, 1);
418 /* ensure that no TB jump will be modified as
419 the program flow was changed */
420 #if defined(__sparc__) && !defined(HOST_SOLARIS)
421 tmp_T0 = 0;
422 #else
423 T0 = 0;
424 #endif
425 #if !defined(CONFIG_USER_ONLY)
426 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
427 (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
428 int intno;
429 /* FIXME: this should respect TPR */
430 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
431 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl),
432 ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK);
433 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
434 if (loglevel & CPU_LOG_TB_IN_ASM)
435 fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno);
436 do_interrupt(intno, 0, 0, -1, 1);
437 #if defined(__sparc__) && !defined(HOST_SOLARIS)
438 tmp_T0 = 0;
439 #else
440 T0 = 0;
441 #endif
442 #endif
443 }
444 #elif defined(TARGET_PPC)
445 #if 0
446 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
447 cpu_ppc_reset(env);
448 }
449 #endif
450 if (interrupt_request & CPU_INTERRUPT_HARD) {
451 ppc_hw_interrupt(env);
452 if (env->pending_interrupts == 0)
453 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
454 #if defined(__sparc__) && !defined(HOST_SOLARIS)
455 tmp_T0 = 0;
456 #else
457 T0 = 0;
458 #endif
459 }
460 #elif defined(TARGET_MIPS)
461 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
462 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
463 (env->CP0_Status & (1 << CP0St_IE)) &&
464 !(env->CP0_Status & (1 << CP0St_EXL)) &&
465 !(env->CP0_Status & (1 << CP0St_ERL)) &&
466 !(env->hflags & MIPS_HFLAG_DM)) {
467 /* Raise it */
468 env->exception_index = EXCP_EXT_INTERRUPT;
469 env->error_code = 0;
470 do_interrupt(env);
471 #if defined(__sparc__) && !defined(HOST_SOLARIS)
472 tmp_T0 = 0;
473 #else
474 T0 = 0;
475 #endif
476 }
477 #elif defined(TARGET_SPARC)
478 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
479 (env->psret != 0)) {
480 int pil = env->interrupt_index & 15;
481 int type = env->interrupt_index & 0xf0;
482
483 if (((type == TT_EXTINT) &&
484 (pil == 15 || pil > env->psrpil)) ||
485 type != TT_EXTINT) {
486 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
487 do_interrupt(env->interrupt_index);
488 env->interrupt_index = 0;
489 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
490 cpu_check_irqs(env);
491 #endif
492 #if defined(__sparc__) && !defined(HOST_SOLARIS)
493 tmp_T0 = 0;
494 #else
495 T0 = 0;
496 #endif
497 }
498 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
499 //do_interrupt(0, 0, 0, 0, 0);
500 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
501 }
502 #elif defined(TARGET_ARM)
503 if (interrupt_request & CPU_INTERRUPT_FIQ
504 && !(env->uncached_cpsr & CPSR_F)) {
505 env->exception_index = EXCP_FIQ;
506 do_interrupt(env);
507 }
508 if (interrupt_request & CPU_INTERRUPT_HARD
509 && !(env->uncached_cpsr & CPSR_I)) {
510 env->exception_index = EXCP_IRQ;
511 do_interrupt(env);
512 }
513 #elif defined(TARGET_SH4)
514 /* XXXXX */
515 #elif defined(TARGET_ALPHA)
516 if (interrupt_request & CPU_INTERRUPT_HARD) {
517 do_interrupt(env);
518 }
519 #elif defined(TARGET_M68K)
520 if (interrupt_request & CPU_INTERRUPT_HARD
521 && ((env->sr & SR_I) >> SR_I_SHIFT)
522 < env->pending_level) {
523 /* Real hardware gets the interrupt vector via an
524 IACK cycle at this point. Current emulated
525 hardware doesn't rely on this, so we
526 provide/save the vector when the interrupt is
527 first signalled. */
528 env->exception_index = env->pending_vector;
529 do_interrupt(1);
530 }
531 #endif
532 /* Don't use the cached interupt_request value,
533 do_interrupt may have updated the EXITTB flag. */
534 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
535 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
536 /* ensure that no TB jump will be modified as
537 the program flow was changed */
538 #if defined(__sparc__) && !defined(HOST_SOLARIS)
539 tmp_T0 = 0;
540 #else
541 T0 = 0;
542 #endif
543 }
544 if (interrupt_request & CPU_INTERRUPT_EXIT) {
545 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
546 env->exception_index = EXCP_INTERRUPT;
547 cpu_loop_exit();
548 }
549 }
550 #ifdef DEBUG_EXEC
551 if ((loglevel & CPU_LOG_TB_CPU)) {
552 /* restore flags in standard format */
553 regs_to_env();
554 #if defined(TARGET_I386)
555 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
556 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
557 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
558 #elif defined(TARGET_ARM)
559 cpu_dump_state(env, logfile, fprintf, 0);
560 #elif defined(TARGET_SPARC)
561 REGWPTR = env->regbase + (env->cwp * 16);
562 env->regwptr = REGWPTR;
563 cpu_dump_state(env, logfile, fprintf, 0);
564 #elif defined(TARGET_PPC)
565 cpu_dump_state(env, logfile, fprintf, 0);
566 #elif defined(TARGET_M68K)
567 cpu_m68k_flush_flags(env, env->cc_op);
568 env->cc_op = CC_OP_FLAGS;
569 env->sr = (env->sr & 0xffe0)
570 | env->cc_dest | (env->cc_x << 4);
571 cpu_dump_state(env, logfile, fprintf, 0);
572 #elif defined(TARGET_MIPS)
573 cpu_dump_state(env, logfile, fprintf, 0);
574 #elif defined(TARGET_SH4)
575 cpu_dump_state(env, logfile, fprintf, 0);
576 #elif defined(TARGET_ALPHA)
577 cpu_dump_state(env, logfile, fprintf, 0);
578 #else
579 #error unsupported target CPU
580 #endif
581 }
582 #endif
583 tb = tb_find_fast();
584 #ifdef DEBUG_EXEC
585 if ((loglevel & CPU_LOG_EXEC)) {
586 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
587 (long)tb->tc_ptr, tb->pc,
588 lookup_symbol(tb->pc));
589 }
590 #endif
591 #if defined(__sparc__) && !defined(HOST_SOLARIS)
592 T0 = tmp_T0;
593 #endif
594 /* see if we can patch the calling TB. When the TB
595 spans two pages, we cannot safely do a direct
596 jump. */
597 {
598 if (T0 != 0 &&
599 #if USE_KQEMU
600 (env->kqemu_enabled != 2) &&
601 #endif
602 tb->page_addr[1] == -1
603 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
604 && (tb->cflags & CF_CODE_COPY) ==
605 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
606 #endif
607 ) {
608 spin_lock(&tb_lock);
609 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
610 #if defined(USE_CODE_COPY)
611 /* propagates the FP use info */
612 ((TranslationBlock *)(T0 & ~3))->cflags |=
613 (tb->cflags & CF_FP_USED);
614 #endif
615 spin_unlock(&tb_lock);
616 }
617 }
618 tc_ptr = tb->tc_ptr;
619 env->current_tb = tb;
620 /* execute the generated code */
621 gen_func = (void *)tc_ptr;
622 #if defined(__sparc__)
623 __asm__ __volatile__("call %0\n\t"
624 "mov %%o7,%%i0"
625 : /* no outputs */
626 : "r" (gen_func)
627 : "i0", "i1", "i2", "i3", "i4", "i5",
628 "o0", "o1", "o2", "o3", "o4", "o5",
629 "l0", "l1", "l2", "l3", "l4", "l5",
630 "l6", "l7");
631 #elif defined(__arm__)
632 asm volatile ("mov pc, %0\n\t"
633 ".global exec_loop\n\t"
634 "exec_loop:\n\t"
635 : /* no outputs */
636 : "r" (gen_func)
637 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
638 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
639 {
640 if (!(tb->cflags & CF_CODE_COPY)) {
641 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
642 save_native_fp_state(env);
643 }
644 gen_func();
645 } else {
646 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
647 restore_native_fp_state(env);
648 }
649 /* we work with native eflags */
650 CC_SRC = cc_table[CC_OP].compute_all();
651 CC_OP = CC_OP_EFLAGS;
652 asm(".globl exec_loop\n"
653 "\n"
654 "debug1:\n"
655 " pushl %%ebp\n"
656 " fs movl %10, %9\n"
657 " fs movl %11, %%eax\n"
658 " andl $0x400, %%eax\n"
659 " fs orl %8, %%eax\n"
660 " pushl %%eax\n"
661 " popf\n"
662 " fs movl %%esp, %12\n"
663 " fs movl %0, %%eax\n"
664 " fs movl %1, %%ecx\n"
665 " fs movl %2, %%edx\n"
666 " fs movl %3, %%ebx\n"
667 " fs movl %4, %%esp\n"
668 " fs movl %5, %%ebp\n"
669 " fs movl %6, %%esi\n"
670 " fs movl %7, %%edi\n"
671 " fs jmp *%9\n"
672 "exec_loop:\n"
673 " fs movl %%esp, %4\n"
674 " fs movl %12, %%esp\n"
675 " fs movl %%eax, %0\n"
676 " fs movl %%ecx, %1\n"
677 " fs movl %%edx, %2\n"
678 " fs movl %%ebx, %3\n"
679 " fs movl %%ebp, %5\n"
680 " fs movl %%esi, %6\n"
681 " fs movl %%edi, %7\n"
682 " pushf\n"
683 " popl %%eax\n"
684 " movl %%eax, %%ecx\n"
685 " andl $0x400, %%ecx\n"
686 " shrl $9, %%ecx\n"
687 " andl $0x8d5, %%eax\n"
688 " fs movl %%eax, %8\n"
689 " movl $1, %%eax\n"
690 " subl %%ecx, %%eax\n"
691 " fs movl %%eax, %11\n"
692 " fs movl %9, %%ebx\n" /* get T0 value */
693 " popl %%ebp\n"
694 :
695 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
696 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
697 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
698 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
699 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
700 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
701 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
702 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
703 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
704 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
705 "a" (gen_func),
706 "m" (*(uint8_t *)offsetof(CPUState, df)),
707 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
708 : "%ecx", "%edx"
709 );
710 }
711 }
712 #elif defined(__ia64)
713 struct fptr {
714 void *ip;
715 void *gp;
716 } fp;
717
718 fp.ip = tc_ptr;
719 fp.gp = code_gen_buffer + 2 * (1 << 20);
720 (*(void (*)(void)) &fp)();
721 #else
722 gen_func();
723 #endif
724 env->current_tb = NULL;
725 /* reset soft MMU for next block (it can currently
726 only be set by a memory fault) */
727 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
728 if (env->hflags & HF_SOFTMMU_MASK) {
729 env->hflags &= ~HF_SOFTMMU_MASK;
730 /* do not allow linking to another block */
731 T0 = 0;
732 }
733 #endif
734 #if defined(USE_KQEMU)
735 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
736 if (kqemu_is_ok(env) &&
737 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
738 cpu_loop_exit();
739 }
740 #endif
741 } /* for(;;) */
742 } else {
743 env_to_regs();
744 }
745 } /* for(;;) */
746
747
748 #if defined(TARGET_I386)
749 #if defined(USE_CODE_COPY)
750 if (env->native_fp_regs) {
751 save_native_fp_state(env);
752 }
753 #endif
754 /* restore flags in standard format */
755 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
756 #elif defined(TARGET_ARM)
757 /* XXX: Save/restore host fpu exception state?. */
758 #elif defined(TARGET_SPARC)
759 #if defined(reg_REGWPTR)
760 REGWPTR = saved_regwptr;
761 #endif
762 #elif defined(TARGET_PPC)
763 #elif defined(TARGET_M68K)
764 cpu_m68k_flush_flags(env, env->cc_op);
765 env->cc_op = CC_OP_FLAGS;
766 env->sr = (env->sr & 0xffe0)
767 | env->cc_dest | (env->cc_x << 4);
768 #elif defined(TARGET_MIPS)
769 #elif defined(TARGET_SH4)
770 #elif defined(TARGET_ALPHA)
771 /* XXXXX */
772 #else
773 #error unsupported target CPU
774 #endif
775
776 /* restore global registers */
777 #if defined(__sparc__) && !defined(HOST_SOLARIS)
778 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
779 #endif
780 #include "hostregs_helper.h"
781
782 /* fail safe : never use cpu_single_env outside cpu_exec() */
783 cpu_single_env = NULL;
784 return ret;
785 }
786
787 /* must only be called from the generated code as an exception can be
788 generated */
789 void tb_invalidate_page_range(target_ulong start, target_ulong end)
790 {
791 /* XXX: cannot enable it yet because it yields to MMU exception
792 where NIP != read address on PowerPC */
793 #if 0
794 target_ulong phys_addr;
795 phys_addr = get_phys_addr_code(env, start);
796 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
797 #endif
798 }
799
800 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
801
802 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
803 {
804 CPUX86State *saved_env;
805
806 saved_env = env;
807 env = s;
808 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
809 selector &= 0xffff;
810 cpu_x86_load_seg_cache(env, seg_reg, selector,
811 (selector << 4), 0xffff, 0);
812 } else {
813 load_seg(seg_reg, selector);
814 }
815 env = saved_env;
816 }
817
818 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
819 {
820 CPUX86State *saved_env;
821
822 saved_env = env;
823 env = s;
824
825 helper_fsave((target_ulong)ptr, data32);
826
827 env = saved_env;
828 }
829
830 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
831 {
832 CPUX86State *saved_env;
833
834 saved_env = env;
835 env = s;
836
837 helper_frstor((target_ulong)ptr, data32);
838
839 env = saved_env;
840 }
841
842 #endif /* TARGET_I386 */
843
844 #if !defined(CONFIG_SOFTMMU)
845
846 #if defined(TARGET_I386)
847
848 /* 'pc' is the host PC at which the exception was raised. 'address' is
849 the effective address of the memory exception. 'is_write' is 1 if a
850 write caused the exception and otherwise 0'. 'old_set' is the
851 signal set which should be restored */
852 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
853 int is_write, sigset_t *old_set,
854 void *puc)
855 {
856 TranslationBlock *tb;
857 int ret;
858
859 if (cpu_single_env)
860 env = cpu_single_env; /* XXX: find a correct solution for multithread */
861 #if defined(DEBUG_SIGNAL)
862 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
863 pc, address, is_write, *(unsigned long *)old_set);
864 #endif
865 /* XXX: locking issue */
866 if (is_write && page_unprotect(h2g(address), pc, puc)) {
867 return 1;
868 }
869
870 /* see if it is an MMU fault */
871 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
872 ((env->hflags & HF_CPL_MASK) == 3), 0);
873 if (ret < 0)
874 return 0; /* not an MMU fault */
875 if (ret == 0)
876 return 1; /* the MMU fault was handled without causing real CPU fault */
877 /* now we have a real cpu fault */
878 tb = tb_find_pc(pc);
879 if (tb) {
880 /* the PC is inside the translated code. It means that we have
881 a virtual CPU fault */
882 cpu_restore_state(tb, env, pc, puc);
883 }
884 if (ret == 1) {
885 #if 0
886 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
887 env->eip, env->cr[2], env->error_code);
888 #endif
889 /* we restore the process signal mask as the sigreturn should
890 do it (XXX: use sigsetjmp) */
891 sigprocmask(SIG_SETMASK, old_set, NULL);
892 raise_exception_err(env->exception_index, env->error_code);
893 } else {
894 /* activate soft MMU for this block */
895 env->hflags |= HF_SOFTMMU_MASK;
896 cpu_resume_from_signal(env, puc);
897 }
898 /* never comes here */
899 return 1;
900 }
901
902 #elif defined(TARGET_ARM)
903 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
904 int is_write, sigset_t *old_set,
905 void *puc)
906 {
907 TranslationBlock *tb;
908 int ret;
909
910 if (cpu_single_env)
911 env = cpu_single_env; /* XXX: find a correct solution for multithread */
912 #if defined(DEBUG_SIGNAL)
913 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
914 pc, address, is_write, *(unsigned long *)old_set);
915 #endif
916 /* XXX: locking issue */
917 if (is_write && page_unprotect(h2g(address), pc, puc)) {
918 return 1;
919 }
920 /* see if it is an MMU fault */
921 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
922 if (ret < 0)
923 return 0; /* not an MMU fault */
924 if (ret == 0)
925 return 1; /* the MMU fault was handled without causing real CPU fault */
926 /* now we have a real cpu fault */
927 tb = tb_find_pc(pc);
928 if (tb) {
929 /* the PC is inside the translated code. It means that we have
930 a virtual CPU fault */
931 cpu_restore_state(tb, env, pc, puc);
932 }
933 /* we restore the process signal mask as the sigreturn should
934 do it (XXX: use sigsetjmp) */
935 sigprocmask(SIG_SETMASK, old_set, NULL);
936 cpu_loop_exit();
937 }
938 #elif defined(TARGET_SPARC)
939 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
940 int is_write, sigset_t *old_set,
941 void *puc)
942 {
943 TranslationBlock *tb;
944 int ret;
945
946 if (cpu_single_env)
947 env = cpu_single_env; /* XXX: find a correct solution for multithread */
948 #if defined(DEBUG_SIGNAL)
949 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
950 pc, address, is_write, *(unsigned long *)old_set);
951 #endif
952 /* XXX: locking issue */
953 if (is_write && page_unprotect(h2g(address), pc, puc)) {
954 return 1;
955 }
956 /* see if it is an MMU fault */
957 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
958 if (ret < 0)
959 return 0; /* not an MMU fault */
960 if (ret == 0)
961 return 1; /* the MMU fault was handled without causing real CPU fault */
962 /* now we have a real cpu fault */
963 tb = tb_find_pc(pc);
964 if (tb) {
965 /* the PC is inside the translated code. It means that we have
966 a virtual CPU fault */
967 cpu_restore_state(tb, env, pc, puc);
968 }
969 /* we restore the process signal mask as the sigreturn should
970 do it (XXX: use sigsetjmp) */
971 sigprocmask(SIG_SETMASK, old_set, NULL);
972 cpu_loop_exit();
973 }
974 #elif defined (TARGET_PPC)
975 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
976 int is_write, sigset_t *old_set,
977 void *puc)
978 {
979 TranslationBlock *tb;
980 int ret;
981
982 if (cpu_single_env)
983 env = cpu_single_env; /* XXX: find a correct solution for multithread */
984 #if defined(DEBUG_SIGNAL)
985 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
986 pc, address, is_write, *(unsigned long *)old_set);
987 #endif
988 /* XXX: locking issue */
989 if (is_write && page_unprotect(h2g(address), pc, puc)) {
990 return 1;
991 }
992
993 /* see if it is an MMU fault */
994 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
995 if (ret < 0)
996 return 0; /* not an MMU fault */
997 if (ret == 0)
998 return 1; /* the MMU fault was handled without causing real CPU fault */
999
1000 /* now we have a real cpu fault */
1001 tb = tb_find_pc(pc);
1002 if (tb) {
1003 /* the PC is inside the translated code. It means that we have
1004 a virtual CPU fault */
1005 cpu_restore_state(tb, env, pc, puc);
1006 }
1007 if (ret == 1) {
1008 #if 0
1009 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1010 env->nip, env->error_code, tb);
1011 #endif
1012 /* we restore the process signal mask as the sigreturn should
1013 do it (XXX: use sigsetjmp) */
1014 sigprocmask(SIG_SETMASK, old_set, NULL);
1015 do_raise_exception_err(env->exception_index, env->error_code);
1016 } else {
1017 /* activate soft MMU for this block */
1018 cpu_resume_from_signal(env, puc);
1019 }
1020 /* never comes here */
1021 return 1;
1022 }
1023
1024 #elif defined(TARGET_M68K)
1025 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1026 int is_write, sigset_t *old_set,
1027 void *puc)
1028 {
1029 TranslationBlock *tb;
1030 int ret;
1031
1032 if (cpu_single_env)
1033 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1034 #if defined(DEBUG_SIGNAL)
1035 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1036 pc, address, is_write, *(unsigned long *)old_set);
1037 #endif
1038 /* XXX: locking issue */
1039 if (is_write && page_unprotect(address, pc, puc)) {
1040 return 1;
1041 }
1042 /* see if it is an MMU fault */
1043 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1044 if (ret < 0)
1045 return 0; /* not an MMU fault */
1046 if (ret == 0)
1047 return 1; /* the MMU fault was handled without causing real CPU fault */
1048 /* now we have a real cpu fault */
1049 tb = tb_find_pc(pc);
1050 if (tb) {
1051 /* the PC is inside the translated code. It means that we have
1052 a virtual CPU fault */
1053 cpu_restore_state(tb, env, pc, puc);
1054 }
1055 /* we restore the process signal mask as the sigreturn should
1056 do it (XXX: use sigsetjmp) */
1057 sigprocmask(SIG_SETMASK, old_set, NULL);
1058 cpu_loop_exit();
1059 /* never comes here */
1060 return 1;
1061 }
1062
1063 #elif defined (TARGET_MIPS)
1064 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1065 int is_write, sigset_t *old_set,
1066 void *puc)
1067 {
1068 TranslationBlock *tb;
1069 int ret;
1070
1071 if (cpu_single_env)
1072 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1073 #if defined(DEBUG_SIGNAL)
1074 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1075 pc, address, is_write, *(unsigned long *)old_set);
1076 #endif
1077 /* XXX: locking issue */
1078 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1079 return 1;
1080 }
1081
1082 /* see if it is an MMU fault */
1083 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1084 if (ret < 0)
1085 return 0; /* not an MMU fault */
1086 if (ret == 0)
1087 return 1; /* the MMU fault was handled without causing real CPU fault */
1088
1089 /* now we have a real cpu fault */
1090 tb = tb_find_pc(pc);
1091 if (tb) {
1092 /* the PC is inside the translated code. It means that we have
1093 a virtual CPU fault */
1094 cpu_restore_state(tb, env, pc, puc);
1095 }
1096 if (ret == 1) {
1097 #if 0
1098 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1099 env->PC, env->error_code, tb);
1100 #endif
1101 /* we restore the process signal mask as the sigreturn should
1102 do it (XXX: use sigsetjmp) */
1103 sigprocmask(SIG_SETMASK, old_set, NULL);
1104 do_raise_exception_err(env->exception_index, env->error_code);
1105 } else {
1106 /* activate soft MMU for this block */
1107 cpu_resume_from_signal(env, puc);
1108 }
1109 /* never comes here */
1110 return 1;
1111 }
1112
1113 #elif defined (TARGET_SH4)
1114 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1115 int is_write, sigset_t *old_set,
1116 void *puc)
1117 {
1118 TranslationBlock *tb;
1119 int ret;
1120
1121 if (cpu_single_env)
1122 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1123 #if defined(DEBUG_SIGNAL)
1124 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1125 pc, address, is_write, *(unsigned long *)old_set);
1126 #endif
1127 /* XXX: locking issue */
1128 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1129 return 1;
1130 }
1131
1132 /* see if it is an MMU fault */
1133 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1134 if (ret < 0)
1135 return 0; /* not an MMU fault */
1136 if (ret == 0)
1137 return 1; /* the MMU fault was handled without causing real CPU fault */
1138
1139 /* now we have a real cpu fault */
1140 tb = tb_find_pc(pc);
1141 if (tb) {
1142 /* the PC is inside the translated code. It means that we have
1143 a virtual CPU fault */
1144 cpu_restore_state(tb, env, pc, puc);
1145 }
1146 #if 0
1147 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1148 env->nip, env->error_code, tb);
1149 #endif
1150 /* we restore the process signal mask as the sigreturn should
1151 do it (XXX: use sigsetjmp) */
1152 sigprocmask(SIG_SETMASK, old_set, NULL);
1153 cpu_loop_exit();
1154 /* never comes here */
1155 return 1;
1156 }
1157
1158 #elif defined (TARGET_ALPHA)
1159 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1160 int is_write, sigset_t *old_set,
1161 void *puc)
1162 {
1163 TranslationBlock *tb;
1164 int ret;
1165
1166 if (cpu_single_env)
1167 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1168 #if defined(DEBUG_SIGNAL)
1169 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1170 pc, address, is_write, *(unsigned long *)old_set);
1171 #endif
1172 /* XXX: locking issue */
1173 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1174 return 1;
1175 }
1176
1177 /* see if it is an MMU fault */
1178 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0);
1179 if (ret < 0)
1180 return 0; /* not an MMU fault */
1181 if (ret == 0)
1182 return 1; /* the MMU fault was handled without causing real CPU fault */
1183
1184 /* now we have a real cpu fault */
1185 tb = tb_find_pc(pc);
1186 if (tb) {
1187 /* the PC is inside the translated code. It means that we have
1188 a virtual CPU fault */
1189 cpu_restore_state(tb, env, pc, puc);
1190 }
1191 #if 0
1192 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1193 env->nip, env->error_code, tb);
1194 #endif
1195 /* we restore the process signal mask as the sigreturn should
1196 do it (XXX: use sigsetjmp) */
1197 sigprocmask(SIG_SETMASK, old_set, NULL);
1198 cpu_loop_exit();
1199 /* never comes here */
1200 return 1;
1201 }
1202 #else
1203 #error unsupported target CPU
1204 #endif
1205
1206 #if defined(__i386__)
1207
1208 #if defined(__APPLE__)
1209 # include <sys/ucontext.h>
1210
1211 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1212 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1213 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1214 #else
1215 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1216 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1217 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1218 #endif
1219
1220 #if defined(USE_CODE_COPY)
1221 static void cpu_send_trap(unsigned long pc, int trap,
1222 struct ucontext *uc)
1223 {
1224 TranslationBlock *tb;
1225
1226 if (cpu_single_env)
1227 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1228 /* now we have a real cpu fault */
1229 tb = tb_find_pc(pc);
1230 if (tb) {
1231 /* the PC is inside the translated code. It means that we have
1232 a virtual CPU fault */
1233 cpu_restore_state(tb, env, pc, uc);
1234 }
1235 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1236 raise_exception_err(trap, env->error_code);
1237 }
1238 #endif
1239
1240 int cpu_signal_handler(int host_signum, void *pinfo,
1241 void *puc)
1242 {
1243 siginfo_t *info = pinfo;
1244 struct ucontext *uc = puc;
1245 unsigned long pc;
1246 int trapno;
1247
1248 #ifndef REG_EIP
1249 /* for glibc 2.1 */
1250 #define REG_EIP EIP
1251 #define REG_ERR ERR
1252 #define REG_TRAPNO TRAPNO
1253 #endif
1254 pc = EIP_sig(uc);
1255 trapno = TRAP_sig(uc);
1256 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1257 if (trapno == 0x00 || trapno == 0x05) {
1258 /* send division by zero or bound exception */
1259 cpu_send_trap(pc, trapno, uc);
1260 return 1;
1261 } else
1262 #endif
1263 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1264 trapno == 0xe ?
1265 (ERROR_sig(uc) >> 1) & 1 : 0,
1266 &uc->uc_sigmask, puc);
1267 }
1268
1269 #elif defined(__x86_64__)
1270
1271 int cpu_signal_handler(int host_signum, void *pinfo,
1272 void *puc)
1273 {
1274 siginfo_t *info = pinfo;
1275 struct ucontext *uc = puc;
1276 unsigned long pc;
1277
1278 pc = uc->uc_mcontext.gregs[REG_RIP];
1279 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1280 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1281 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1282 &uc->uc_sigmask, puc);
1283 }
1284
1285 #elif defined(__powerpc__)
1286
1287 /***********************************************************************
1288 * signal context platform-specific definitions
1289 * From Wine
1290 */
1291 #ifdef linux
1292 /* All Registers access - only for local access */
1293 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1294 /* Gpr Registers access */
1295 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1296 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1297 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1298 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1299 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1300 # define LR_sig(context) REG_sig(link, context) /* Link register */
1301 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1302 /* Float Registers access */
1303 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1304 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1305 /* Exception Registers access */
1306 # define DAR_sig(context) REG_sig(dar, context)
1307 # define DSISR_sig(context) REG_sig(dsisr, context)
1308 # define TRAP_sig(context) REG_sig(trap, context)
1309 #endif /* linux */
1310
1311 #ifdef __APPLE__
1312 # include <sys/ucontext.h>
1313 typedef struct ucontext SIGCONTEXT;
1314 /* All Registers access - only for local access */
1315 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1316 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1317 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1318 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1319 /* Gpr Registers access */
1320 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1321 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1322 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1323 # define CTR_sig(context) REG_sig(ctr, context)
1324 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1325 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1326 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1327 /* Float Registers access */
1328 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1329 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1330 /* Exception Registers access */
1331 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1332 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1333 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1334 #endif /* __APPLE__ */
1335
1336 int cpu_signal_handler(int host_signum, void *pinfo,
1337 void *puc)
1338 {
1339 siginfo_t *info = pinfo;
1340 struct ucontext *uc = puc;
1341 unsigned long pc;
1342 int is_write;
1343
1344 pc = IAR_sig(uc);
1345 is_write = 0;
1346 #if 0
1347 /* ppc 4xx case */
1348 if (DSISR_sig(uc) & 0x00800000)
1349 is_write = 1;
1350 #else
1351 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1352 is_write = 1;
1353 #endif
1354 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1355 is_write, &uc->uc_sigmask, puc);
1356 }
1357
1358 #elif defined(__alpha__)
1359
1360 int cpu_signal_handler(int host_signum, void *pinfo,
1361 void *puc)
1362 {
1363 siginfo_t *info = pinfo;
1364 struct ucontext *uc = puc;
1365 uint32_t *pc = uc->uc_mcontext.sc_pc;
1366 uint32_t insn = *pc;
1367 int is_write = 0;
1368
1369 /* XXX: need kernel patch to get write flag faster */
1370 switch (insn >> 26) {
1371 case 0x0d: // stw
1372 case 0x0e: // stb
1373 case 0x0f: // stq_u
1374 case 0x24: // stf
1375 case 0x25: // stg
1376 case 0x26: // sts
1377 case 0x27: // stt
1378 case 0x2c: // stl
1379 case 0x2d: // stq
1380 case 0x2e: // stl_c
1381 case 0x2f: // stq_c
1382 is_write = 1;
1383 }
1384
1385 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1386 is_write, &uc->uc_sigmask, puc);
1387 }
1388 #elif defined(__sparc__)
1389
1390 int cpu_signal_handler(int host_signum, void *pinfo,
1391 void *puc)
1392 {
1393 siginfo_t *info = pinfo;
1394 uint32_t *regs = (uint32_t *)(info + 1);
1395 void *sigmask = (regs + 20);
1396 unsigned long pc;
1397 int is_write;
1398 uint32_t insn;
1399
1400 /* XXX: is there a standard glibc define ? */
1401 pc = regs[1];
1402 /* XXX: need kernel patch to get write flag faster */
1403 is_write = 0;
1404 insn = *(uint32_t *)pc;
1405 if ((insn >> 30) == 3) {
1406 switch((insn >> 19) & 0x3f) {
1407 case 0x05: // stb
1408 case 0x06: // sth
1409 case 0x04: // st
1410 case 0x07: // std
1411 case 0x24: // stf
1412 case 0x27: // stdf
1413 case 0x25: // stfsr
1414 is_write = 1;
1415 break;
1416 }
1417 }
1418 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1419 is_write, sigmask, NULL);
1420 }
1421
1422 #elif defined(__arm__)
1423
1424 int cpu_signal_handler(int host_signum, void *pinfo,
1425 void *puc)
1426 {
1427 siginfo_t *info = pinfo;
1428 struct ucontext *uc = puc;
1429 unsigned long pc;
1430 int is_write;
1431
1432 pc = uc->uc_mcontext.gregs[R15];
1433 /* XXX: compute is_write */
1434 is_write = 0;
1435 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1436 is_write,
1437 &uc->uc_sigmask, puc);
1438 }
1439
1440 #elif defined(__mc68000)
1441
1442 int cpu_signal_handler(int host_signum, void *pinfo,
1443 void *puc)
1444 {
1445 siginfo_t *info = pinfo;
1446 struct ucontext *uc = puc;
1447 unsigned long pc;
1448 int is_write;
1449
1450 pc = uc->uc_mcontext.gregs[16];
1451 /* XXX: compute is_write */
1452 is_write = 0;
1453 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1454 is_write,
1455 &uc->uc_sigmask, puc);
1456 }
1457
1458 #elif defined(__ia64)
1459
1460 #ifndef __ISR_VALID
1461 /* This ought to be in <bits/siginfo.h>... */
1462 # define __ISR_VALID 1
1463 #endif
1464
1465 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1466 {
1467 siginfo_t *info = pinfo;
1468 struct ucontext *uc = puc;
1469 unsigned long ip;
1470 int is_write = 0;
1471
1472 ip = uc->uc_mcontext.sc_ip;
1473 switch (host_signum) {
1474 case SIGILL:
1475 case SIGFPE:
1476 case SIGSEGV:
1477 case SIGBUS:
1478 case SIGTRAP:
1479 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1480 /* ISR.W (write-access) is bit 33: */
1481 is_write = (info->si_isr >> 33) & 1;
1482 break;
1483
1484 default:
1485 break;
1486 }
1487 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1488 is_write,
1489 &uc->uc_sigmask, puc);
1490 }
1491
1492 #elif defined(__s390__)
1493
1494 int cpu_signal_handler(int host_signum, void *pinfo,
1495 void *puc)
1496 {
1497 siginfo_t *info = pinfo;
1498 struct ucontext *uc = puc;
1499 unsigned long pc;
1500 int is_write;
1501
1502 pc = uc->uc_mcontext.psw.addr;
1503 /* XXX: compute is_write */
1504 is_write = 0;
1505 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1506 is_write, &uc->uc_sigmask, puc);
1507 }
1508
1509 #elif defined(__mips__)
1510
1511 int cpu_signal_handler(int host_signum, void *pinfo,
1512 void *puc)
1513 {
1514 siginfo_t *info = pinfo;
1515 struct ucontext *uc = puc;
1516 greg_t pc = uc->uc_mcontext.pc;
1517 int is_write;
1518
1519 /* XXX: compute is_write */
1520 is_write = 0;
1521 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1522 is_write, &uc->uc_sigmask, puc);
1523 }
1524
1525 #else
1526
1527 #error host CPU specific signal handler needed
1528
1529 #endif
1530
1531 #endif /* !defined(CONFIG_SOFTMMU) */
Stable branch of Qemu 0.9.1