From 7a9b96cf2165357c4ddc58c37395431adc1f3050 Mon Sep 17 00:00:00 2001 From: aurel32 Date: Thu, 18 Dec 2008 22:42:58 +0000 Subject: [PATCH] target-ppc: add Altivec logical operations Use opc2/opc3 instead of one big xo field. Do this consistency with the rest of translate.c Signed-off-by: Nathan Froyd Signed-off-by: Aurelien Jarno git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6087 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-ppc/translate.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 85fc1b22dc..a2cd9af2b1 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6139,6 +6139,24 @@ GEN_VR_STX(svx, 0x07, 0x07); /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ GEN_VR_STX(svxl, 0x07, 0x0F); +/* Logical operations */ +#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ +GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \ +{ \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ + tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ +} + +GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); +GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); +GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); +GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); +GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); + /*** SPE extension ***/ /* Register moves */ -- 2.11.4.GIT