2 * PowerPC emulation helpers for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include "host-utils.h"
24 #include "helper_regs.h"
27 //#define DEBUG_EXCEPTIONS
28 //#define DEBUG_SOFTWARE_TLB
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
33 void helper_raise_exception_err (uint32_t exception
, uint32_t error_code
)
36 printf("Raise exception %3x code : %d\n", exception
, error_code
);
38 env
->exception_index
= exception
;
39 env
->error_code
= error_code
;
43 void helper_raise_exception (uint32_t exception
)
45 helper_raise_exception_err(exception
, 0);
48 /*****************************************************************************/
49 /* Registers load and stores */
50 target_ulong
helper_load_cr (void)
52 return (env
->crf
[0] << 28) |
62 void helper_store_cr (target_ulong val
, uint32_t mask
)
66 for (i
= 0, sh
= 7; i
< 8; i
++, sh
--) {
68 env
->crf
[i
] = (val
>> (sh
* 4)) & 0xFUL
;
72 /*****************************************************************************/
74 void helper_load_dump_spr (uint32_t sprn
)
77 fprintf(logfile
, "Read SPR %d %03x => " ADDRX
"\n",
78 sprn
, sprn
, env
->spr
[sprn
]);
82 void helper_store_dump_spr (uint32_t sprn
)
85 fprintf(logfile
, "Write SPR %d %03x <= " ADDRX
"\n",
86 sprn
, sprn
, env
->spr
[sprn
]);
90 target_ulong
helper_load_tbl (void)
92 return cpu_ppc_load_tbl(env
);
95 target_ulong
helper_load_tbu (void)
97 return cpu_ppc_load_tbu(env
);
100 target_ulong
helper_load_atbl (void)
102 return cpu_ppc_load_atbl(env
);
105 target_ulong
helper_load_atbu (void)
107 return cpu_ppc_load_atbu(env
);
110 target_ulong
helper_load_601_rtcl (void)
112 return cpu_ppc601_load_rtcl(env
);
115 target_ulong
helper_load_601_rtcu (void)
117 return cpu_ppc601_load_rtcu(env
);
120 #if !defined(CONFIG_USER_ONLY)
121 #if defined (TARGET_PPC64)
122 void helper_store_asr (target_ulong val
)
124 ppc_store_asr(env
, val
);
128 void helper_store_sdr1 (target_ulong val
)
130 ppc_store_sdr1(env
, val
);
133 void helper_store_tbl (target_ulong val
)
135 cpu_ppc_store_tbl(env
, val
);
138 void helper_store_tbu (target_ulong val
)
140 cpu_ppc_store_tbu(env
, val
);
143 void helper_store_atbl (target_ulong val
)
145 cpu_ppc_store_atbl(env
, val
);
148 void helper_store_atbu (target_ulong val
)
150 cpu_ppc_store_atbu(env
, val
);
153 void helper_store_601_rtcl (target_ulong val
)
155 cpu_ppc601_store_rtcl(env
, val
);
158 void helper_store_601_rtcu (target_ulong val
)
160 cpu_ppc601_store_rtcu(env
, val
);
163 target_ulong
helper_load_decr (void)
165 return cpu_ppc_load_decr(env
);
168 void helper_store_decr (target_ulong val
)
170 cpu_ppc_store_decr(env
, val
);
173 void helper_store_hid0_601 (target_ulong val
)
177 hid0
= env
->spr
[SPR_HID0
];
178 if ((val
^ hid0
) & 0x00000008) {
179 /* Change current endianness */
180 env
->hflags
&= ~(1 << MSR_LE
);
181 env
->hflags_nmsr
&= ~(1 << MSR_LE
);
182 env
->hflags_nmsr
|= (1 << MSR_LE
) & (((val
>> 3) & 1) << MSR_LE
);
183 env
->hflags
|= env
->hflags_nmsr
;
185 fprintf(logfile
, "%s: set endianness to %c => " ADDRX
"\n",
186 __func__
, val
& 0x8 ? 'l' : 'b', env
->hflags
);
189 env
->spr
[SPR_HID0
] = (uint32_t)val
;
192 void helper_store_403_pbr (uint32_t num
, target_ulong value
)
194 if (likely(env
->pb
[num
] != value
)) {
195 env
->pb
[num
] = value
;
196 /* Should be optimized */
201 target_ulong
helper_load_40x_pit (void)
203 return load_40x_pit(env
);
206 void helper_store_40x_pit (target_ulong val
)
208 store_40x_pit(env
, val
);
211 void helper_store_40x_dbcr0 (target_ulong val
)
213 store_40x_dbcr0(env
, val
);
216 void helper_store_40x_sler (target_ulong val
)
218 store_40x_sler(env
, val
);
221 void helper_store_booke_tcr (target_ulong val
)
223 store_booke_tcr(env
, val
);
226 void helper_store_booke_tsr (target_ulong val
)
228 store_booke_tsr(env
, val
);
231 void helper_store_ibatu (uint32_t nr
, target_ulong val
)
233 ppc_store_ibatu(env
, nr
, val
);
236 void helper_store_ibatl (uint32_t nr
, target_ulong val
)
238 ppc_store_ibatl(env
, nr
, val
);
241 void helper_store_dbatu (uint32_t nr
, target_ulong val
)
243 ppc_store_dbatu(env
, nr
, val
);
246 void helper_store_dbatl (uint32_t nr
, target_ulong val
)
248 ppc_store_dbatl(env
, nr
, val
);
251 void helper_store_601_batl (uint32_t nr
, target_ulong val
)
253 ppc_store_ibatl_601(env
, nr
, val
);
256 void helper_store_601_batu (uint32_t nr
, target_ulong val
)
258 ppc_store_ibatu_601(env
, nr
, val
);
262 /*****************************************************************************/
263 /* Memory load and stores */
265 static always_inline target_ulong
addr_add(target_ulong addr
, target_long arg
)
267 #if defined(TARGET_PPC64)
269 return (uint32_t)(addr
+ arg
);
275 void helper_lmw (target_ulong addr
, uint32_t reg
)
277 for (; reg
< 32; reg
++) {
279 env
->gpr
[reg
] = bswap32(ldl(addr
));
281 env
->gpr
[reg
] = ldl(addr
);
282 addr
= addr_add(addr
, 4);
286 void helper_stmw (target_ulong addr
, uint32_t reg
)
288 for (; reg
< 32; reg
++) {
290 stl(addr
, bswap32((uint32_t)env
->gpr
[reg
]));
292 stl(addr
, (uint32_t)env
->gpr
[reg
]);
293 addr
= addr_add(addr
, 4);
297 void helper_lsw(target_ulong addr
, uint32_t nb
, uint32_t reg
)
300 for (; nb
> 3; nb
-= 4) {
301 env
->gpr
[reg
] = ldl(addr
);
302 reg
= (reg
+ 1) % 32;
303 addr
= addr_add(addr
, 4);
305 if (unlikely(nb
> 0)) {
307 for (sh
= 24; nb
> 0; nb
--, sh
-= 8) {
308 env
->gpr
[reg
] |= ldub(addr
) << sh
;
309 addr
= addr_add(addr
, 1);
313 /* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
318 void helper_lswx(target_ulong addr
, uint32_t reg
, uint32_t ra
, uint32_t rb
)
320 if (likely(xer_bc
!= 0)) {
321 if (unlikely((ra
!= 0 && reg
< ra
&& (reg
+ xer_bc
) > ra
) ||
322 (reg
< rb
&& (reg
+ xer_bc
) > rb
))) {
323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
325 POWERPC_EXCP_INVAL_LSWX
);
327 helper_lsw(addr
, xer_bc
, reg
);
332 void helper_stsw(target_ulong addr
, uint32_t nb
, uint32_t reg
)
335 for (; nb
> 3; nb
-= 4) {
336 stl(addr
, env
->gpr
[reg
]);
337 reg
= (reg
+ 1) % 32;
338 addr
= addr_add(addr
, 4);
340 if (unlikely(nb
> 0)) {
341 for (sh
= 24; nb
> 0; nb
--, sh
-= 8)
342 stb(addr
, (env
->gpr
[reg
] >> sh
) & 0xFF);
343 addr
= addr_add(addr
, 1);
347 static void do_dcbz(target_ulong addr
, int dcache_line_size
)
349 addr
&= ~(dcache_line_size
- 1);
351 for (i
= 0 ; i
< dcache_line_size
; i
+= 4) {
354 if (env
->reserve
== addr
)
355 env
->reserve
= (target_ulong
)-1ULL;
358 void helper_dcbz(target_ulong addr
)
360 do_dcbz(addr
, env
->dcache_line_size
);
363 void helper_dcbz_970(target_ulong addr
)
365 if (((env
->spr
[SPR_970_HID5
] >> 7) & 0x3) == 1)
368 do_dcbz(addr
, env
->dcache_line_size
);
371 void helper_icbi(target_ulong addr
)
375 addr
&= ~(env
->dcache_line_size
- 1);
376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
382 tb_invalidate_page_range(addr
, addr
+ env
->icache_line_size
);
386 target_ulong
helper_lscbx (target_ulong addr
, uint32_t reg
, uint32_t ra
, uint32_t rb
)
390 for (i
= 0; i
< xer_bc
; i
++) {
392 addr
= addr_add(addr
, 1);
393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg
!= rb
&& (ra
== 0 || reg
!= ra
))) {
395 env
->gpr
[reg
] = (env
->gpr
[reg
] & ~(0xFF << d
)) | (c
<< d
);
397 if (unlikely(c
== xer_cmp
))
399 if (likely(d
!= 0)) {
410 /*****************************************************************************/
411 /* Fixed point operations helpers */
412 #if defined(TARGET_PPC64)
414 /* multiply high word */
415 uint64_t helper_mulhd (uint64_t arg1
, uint64_t arg2
)
419 muls64(&tl
, &th
, arg1
, arg2
);
423 /* multiply high word unsigned */
424 uint64_t helper_mulhdu (uint64_t arg1
, uint64_t arg2
)
428 mulu64(&tl
, &th
, arg1
, arg2
);
432 uint64_t helper_mulldo (uint64_t arg1
, uint64_t arg2
)
437 muls64(&tl
, (uint64_t *)&th
, arg1
, arg2
);
438 /* If th != 0 && th != -1, then we had an overflow */
439 if (likely((uint64_t)(th
+ 1) <= 1)) {
440 env
->xer
&= ~(1 << XER_OV
);
442 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
448 target_ulong
helper_cntlzw (target_ulong t
)
453 #if defined(TARGET_PPC64)
454 target_ulong
helper_cntlzd (target_ulong t
)
460 /* shift right arithmetic helper */
461 target_ulong
helper_sraw (target_ulong value
, target_ulong shift
)
465 if (likely(!(shift
& 0x20))) {
466 if (likely((uint32_t)shift
!= 0)) {
468 ret
= (int32_t)value
>> shift
;
469 if (likely(ret
>= 0 || (value
& ((1 << shift
) - 1)) == 0)) {
470 env
->xer
&= ~(1 << XER_CA
);
472 env
->xer
|= (1 << XER_CA
);
475 ret
= (int32_t)value
;
476 env
->xer
&= ~(1 << XER_CA
);
479 ret
= (int32_t)value
>> 31;
481 env
->xer
|= (1 << XER_CA
);
483 env
->xer
&= ~(1 << XER_CA
);
486 return (target_long
)ret
;
489 #if defined(TARGET_PPC64)
490 target_ulong
helper_srad (target_ulong value
, target_ulong shift
)
494 if (likely(!(shift
& 0x40))) {
495 if (likely((uint64_t)shift
!= 0)) {
497 ret
= (int64_t)value
>> shift
;
498 if (likely(ret
>= 0 || (value
& ((1 << shift
) - 1)) == 0)) {
499 env
->xer
&= ~(1 << XER_CA
);
501 env
->xer
|= (1 << XER_CA
);
504 ret
= (int64_t)value
;
505 env
->xer
&= ~(1 << XER_CA
);
508 ret
= (int64_t)value
>> 63;
510 env
->xer
|= (1 << XER_CA
);
512 env
->xer
&= ~(1 << XER_CA
);
519 target_ulong
helper_popcntb (target_ulong val
)
521 val
= (val
& 0x55555555) + ((val
>> 1) & 0x55555555);
522 val
= (val
& 0x33333333) + ((val
>> 2) & 0x33333333);
523 val
= (val
& 0x0f0f0f0f) + ((val
>> 4) & 0x0f0f0f0f);
527 #if defined(TARGET_PPC64)
528 target_ulong
helper_popcntb_64 (target_ulong val
)
530 val
= (val
& 0x5555555555555555ULL
) + ((val
>> 1) & 0x5555555555555555ULL
);
531 val
= (val
& 0x3333333333333333ULL
) + ((val
>> 2) & 0x3333333333333333ULL
);
532 val
= (val
& 0x0f0f0f0f0f0f0f0fULL
) + ((val
>> 4) & 0x0f0f0f0f0f0f0f0fULL
);
537 /*****************************************************************************/
538 /* Floating point operations helpers */
539 uint64_t helper_float32_to_float64(uint32_t arg
)
544 d
.d
= float32_to_float64(f
.f
, &env
->fp_status
);
548 uint32_t helper_float64_to_float32(uint64_t arg
)
553 f
.f
= float64_to_float32(d
.d
, &env
->fp_status
);
557 static always_inline
int isden (float64 d
)
563 return ((u
.ll
>> 52) & 0x7FF) == 0;
566 #ifdef CONFIG_SOFTFLOAT
567 static always_inline
int isnormal (float64 d
)
573 uint32_t exp
= (u
.ll
>> 52) & 0x7FF;
574 return ((0 < exp
) && (exp
< 0x7FF));
578 uint32_t helper_compute_fprf (uint64_t arg
, uint32_t set_fprf
)
584 isneg
= float64_is_neg(farg
.d
);
585 if (unlikely(float64_is_nan(farg
.d
))) {
586 if (float64_is_signaling_nan(farg
.d
)) {
587 /* Signaling NaN: flags are undefined */
593 } else if (unlikely(float64_is_infinity(farg
.d
))) {
600 if (float64_is_zero(farg
.d
)) {
608 /* Denormalized numbers */
611 /* Normalized numbers */
622 /* We update FPSCR_FPRF */
623 env
->fpscr
&= ~(0x1F << FPSCR_FPRF
);
624 env
->fpscr
|= ret
<< FPSCR_FPRF
;
626 /* We just need fpcc to update Rc1 */
630 /* Floating-point invalid operations exception */
631 static always_inline
uint64_t fload_invalid_op_excp (int op
)
638 case POWERPC_EXCP_FP_VXSNAN
:
639 env
->fpscr
|= 1 << FPSCR_VXSNAN
;
641 case POWERPC_EXCP_FP_VXSOFT
:
642 env
->fpscr
|= 1 << FPSCR_VXSOFT
;
644 case POWERPC_EXCP_FP_VXISI
:
645 /* Magnitude subtraction of infinities */
646 env
->fpscr
|= 1 << FPSCR_VXISI
;
648 case POWERPC_EXCP_FP_VXIDI
:
649 /* Division of infinity by infinity */
650 env
->fpscr
|= 1 << FPSCR_VXIDI
;
652 case POWERPC_EXCP_FP_VXZDZ
:
653 /* Division of zero by zero */
654 env
->fpscr
|= 1 << FPSCR_VXZDZ
;
656 case POWERPC_EXCP_FP_VXIMZ
:
657 /* Multiplication of zero by infinity */
658 env
->fpscr
|= 1 << FPSCR_VXIMZ
;
660 case POWERPC_EXCP_FP_VXVC
:
661 /* Ordered comparison of NaN */
662 env
->fpscr
|= 1 << FPSCR_VXVC
;
663 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
664 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
665 /* We must update the target FPR before raising the exception */
667 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
668 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_VXVC
;
669 /* Update the floating-point enabled exception summary */
670 env
->fpscr
|= 1 << FPSCR_FEX
;
671 /* Exception is differed */
675 case POWERPC_EXCP_FP_VXSQRT
:
676 /* Square root of a negative number */
677 env
->fpscr
|= 1 << FPSCR_VXSQRT
;
679 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
681 /* Set the result to quiet NaN */
682 ret
= 0xFFF8000000000000ULL
;
683 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
684 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
687 case POWERPC_EXCP_FP_VXCVI
:
688 /* Invalid conversion */
689 env
->fpscr
|= 1 << FPSCR_VXCVI
;
690 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
692 /* Set the result to quiet NaN */
693 ret
= 0xFFF8000000000000ULL
;
694 env
->fpscr
&= ~(0xF << FPSCR_FPCC
);
695 env
->fpscr
|= 0x11 << FPSCR_FPCC
;
699 /* Update the floating-point invalid operation summary */
700 env
->fpscr
|= 1 << FPSCR_VX
;
701 /* Update the floating-point exception summary */
702 env
->fpscr
|= 1 << FPSCR_FX
;
704 /* Update the floating-point enabled exception summary */
705 env
->fpscr
|= 1 << FPSCR_FEX
;
706 if (msr_fe0
!= 0 || msr_fe1
!= 0)
707 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_FP
| op
);
712 static always_inline
uint64_t float_zero_divide_excp (uint64_t arg1
, uint64_t arg2
)
714 env
->fpscr
|= 1 << FPSCR_ZX
;
715 env
->fpscr
&= ~((1 << FPSCR_FR
) | (1 << FPSCR_FI
));
716 /* Update the floating-point exception summary */
717 env
->fpscr
|= 1 << FPSCR_FX
;
719 /* Update the floating-point enabled exception summary */
720 env
->fpscr
|= 1 << FPSCR_FEX
;
721 if (msr_fe0
!= 0 || msr_fe1
!= 0) {
722 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
723 POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
);
726 /* Set the result to infinity */
727 arg1
= ((arg1
^ arg2
) & 0x8000000000000000ULL
);
728 arg1
|= 0x7FFULL
<< 52;
733 static always_inline
void float_overflow_excp (void)
735 env
->fpscr
|= 1 << FPSCR_OX
;
736 /* Update the floating-point exception summary */
737 env
->fpscr
|= 1 << FPSCR_FX
;
739 /* XXX: should adjust the result */
740 /* Update the floating-point enabled exception summary */
741 env
->fpscr
|= 1 << FPSCR_FEX
;
742 /* We must update the target FPR before raising the exception */
743 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
744 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
746 env
->fpscr
|= 1 << FPSCR_XX
;
747 env
->fpscr
|= 1 << FPSCR_FI
;
751 static always_inline
void float_underflow_excp (void)
753 env
->fpscr
|= 1 << FPSCR_UX
;
754 /* Update the floating-point exception summary */
755 env
->fpscr
|= 1 << FPSCR_FX
;
757 /* XXX: should adjust the result */
758 /* Update the floating-point enabled exception summary */
759 env
->fpscr
|= 1 << FPSCR_FEX
;
760 /* We must update the target FPR before raising the exception */
761 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
762 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
766 static always_inline
void float_inexact_excp (void)
768 env
->fpscr
|= 1 << FPSCR_XX
;
769 /* Update the floating-point exception summary */
770 env
->fpscr
|= 1 << FPSCR_FX
;
772 /* Update the floating-point enabled exception summary */
773 env
->fpscr
|= 1 << FPSCR_FEX
;
774 /* We must update the target FPR before raising the exception */
775 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
776 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
780 static always_inline
void fpscr_set_rounding_mode (void)
784 /* Set rounding mode */
787 /* Best approximation (round to nearest) */
788 rnd_type
= float_round_nearest_even
;
791 /* Smaller magnitude (round toward zero) */
792 rnd_type
= float_round_to_zero
;
795 /* Round toward +infinite */
796 rnd_type
= float_round_up
;
800 /* Round toward -infinite */
801 rnd_type
= float_round_down
;
804 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
807 void helper_fpscr_clrbit (uint32_t bit
)
811 prev
= (env
->fpscr
>> bit
) & 1;
812 env
->fpscr
&= ~(1 << bit
);
817 fpscr_set_rounding_mode();
825 void helper_fpscr_setbit (uint32_t bit
)
829 prev
= (env
->fpscr
>> bit
) & 1;
830 env
->fpscr
|= 1 << bit
;
834 env
->fpscr
|= 1 << FPSCR_FX
;
838 env
->fpscr
|= 1 << FPSCR_FX
;
843 env
->fpscr
|= 1 << FPSCR_FX
;
848 env
->fpscr
|= 1 << FPSCR_FX
;
853 env
->fpscr
|= 1 << FPSCR_FX
;
866 env
->fpscr
|= 1 << FPSCR_VX
;
867 env
->fpscr
|= 1 << FPSCR_FX
;
874 env
->error_code
= POWERPC_EXCP_FP
;
876 env
->error_code
|= POWERPC_EXCP_FP_VXSNAN
;
878 env
->error_code
|= POWERPC_EXCP_FP_VXISI
;
880 env
->error_code
|= POWERPC_EXCP_FP_VXIDI
;
882 env
->error_code
|= POWERPC_EXCP_FP_VXZDZ
;
884 env
->error_code
|= POWERPC_EXCP_FP_VXIMZ
;
886 env
->error_code
|= POWERPC_EXCP_FP_VXVC
;
888 env
->error_code
|= POWERPC_EXCP_FP_VXSOFT
;
890 env
->error_code
|= POWERPC_EXCP_FP_VXSQRT
;
892 env
->error_code
|= POWERPC_EXCP_FP_VXCVI
;
899 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_OX
;
906 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_UX
;
913 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_ZX
;
920 env
->error_code
= POWERPC_EXCP_FP
| POWERPC_EXCP_FP_XX
;
926 fpscr_set_rounding_mode();
931 /* Update the floating-point enabled exception summary */
932 env
->fpscr
|= 1 << FPSCR_FEX
;
933 /* We have to update Rc1 before raising the exception */
934 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
940 void helper_store_fpscr (uint64_t arg
, uint32_t mask
)
943 * We use only the 32 LSB of the incoming fpr
951 new |= prev
& 0x60000000;
952 for (i
= 0; i
< 8; i
++) {
953 if (mask
& (1 << i
)) {
954 env
->fpscr
&= ~(0xF << (4 * i
));
955 env
->fpscr
|= new & (0xF << (4 * i
));
958 /* Update VX and FEX */
960 env
->fpscr
|= 1 << FPSCR_VX
;
962 env
->fpscr
&= ~(1 << FPSCR_VX
);
963 if ((fpscr_ex
& fpscr_eex
) != 0) {
964 env
->fpscr
|= 1 << FPSCR_FEX
;
965 env
->exception_index
= POWERPC_EXCP_PROGRAM
;
966 /* XXX: we should compute it properly */
967 env
->error_code
= POWERPC_EXCP_FP
;
970 env
->fpscr
&= ~(1 << FPSCR_FEX
);
971 fpscr_set_rounding_mode();
974 void helper_float_check_status (void)
976 #ifdef CONFIG_SOFTFLOAT
977 if (env
->exception_index
== POWERPC_EXCP_PROGRAM
&&
978 (env
->error_code
& POWERPC_EXCP_FP
)) {
979 /* Differred floating-point exception after target FPR update */
980 if (msr_fe0
!= 0 || msr_fe1
!= 0)
981 helper_raise_exception_err(env
->exception_index
, env
->error_code
);
983 int status
= get_float_exception_flags(&env
->fp_status
);
984 if (status
& float_flag_overflow
) {
985 float_overflow_excp();
986 } else if (status
& float_flag_underflow
) {
987 float_underflow_excp();
988 } else if (status
& float_flag_inexact
) {
989 float_inexact_excp();
993 if (env
->exception_index
== POWERPC_EXCP_PROGRAM
&&
994 (env
->error_code
& POWERPC_EXCP_FP
)) {
995 /* Differred floating-point exception after target FPR update */
996 if (msr_fe0
!= 0 || msr_fe1
!= 0)
997 helper_raise_exception_err(env
->exception_index
, env
->error_code
);
1002 #ifdef CONFIG_SOFTFLOAT
1003 void helper_reset_fpstatus (void)
1005 set_float_exception_flags(0, &env
->fp_status
);
1010 uint64_t helper_fadd (uint64_t arg1
, uint64_t arg2
)
1012 CPU_DoubleU farg1
, farg2
;
1016 #if USE_PRECISE_EMULATION
1017 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1018 float64_is_signaling_nan(farg2
.d
))) {
1020 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1021 } else if (unlikely(float64_is_infinity(farg1
.d
) && float64_is_infinity(farg2
.d
) &&
1022 float64_is_neg(farg1
.d
) != float64_is_neg(farg2
.d
))) {
1023 /* Magnitude subtraction of infinities */
1024 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1026 farg1
.d
= float64_add(farg1
.d
, farg2
.d
, &env
->fp_status
);
1029 farg1
.d
= float64_add(farg1
.d
, farg2
.d
, &env
->fp_status
);
1035 uint64_t helper_fsub (uint64_t arg1
, uint64_t arg2
)
1037 CPU_DoubleU farg1
, farg2
;
1041 #if USE_PRECISE_EMULATION
1043 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1044 float64_is_signaling_nan(farg2
.d
))) {
1045 /* sNaN subtraction */
1046 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1047 } else if (unlikely(float64_is_infinity(farg1
.d
) && float64_is_infinity(farg2
.d
) &&
1048 float64_is_neg(farg1
.d
) == float64_is_neg(farg2
.d
))) {
1049 /* Magnitude subtraction of infinities */
1050 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1052 farg1
.d
= float64_sub(farg1
.d
, farg2
.d
, &env
->fp_status
);
1056 farg1
.d
= float64_sub(farg1
.d
, farg2
.d
, &env
->fp_status
);
1062 uint64_t helper_fmul (uint64_t arg1
, uint64_t arg2
)
1064 CPU_DoubleU farg1
, farg2
;
1068 #if USE_PRECISE_EMULATION
1069 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1070 float64_is_signaling_nan(farg2
.d
))) {
1071 /* sNaN multiplication */
1072 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1073 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1074 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1075 /* Multiplication of zero by infinity */
1076 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1078 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1081 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1087 uint64_t helper_fdiv (uint64_t arg1
, uint64_t arg2
)
1089 CPU_DoubleU farg1
, farg2
;
1093 #if USE_PRECISE_EMULATION
1094 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1095 float64_is_signaling_nan(farg2
.d
))) {
1097 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1098 } else if (unlikely(float64_is_infinity(farg1
.d
) && float64_is_infinity(farg2
.d
))) {
1099 /* Division of infinity by infinity */
1100 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI
);
1101 } else if (unlikely(!float64_is_nan(farg1
.d
) && float64_is_zero(farg2
.d
))) {
1102 if (float64_is_zero(farg1
.d
)) {
1103 /* Division of zero by zero */
1104 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ
);
1106 /* Division by zero */
1107 farg1
.ll
= float_zero_divide_excp(farg1
.d
, farg2
.d
);
1110 farg1
.d
= float64_div(farg1
.d
, farg2
.d
, &env
->fp_status
);
1113 farg1
.d
= float64_div(farg1
.d
, farg2
.d
, &env
->fp_status
);
1119 uint64_t helper_fabs (uint64_t arg
)
1124 farg
.d
= float64_abs(farg
.d
);
1129 uint64_t helper_fnabs (uint64_t arg
)
1134 farg
.d
= float64_abs(farg
.d
);
1135 farg
.d
= float64_chs(farg
.d
);
1140 uint64_t helper_fneg (uint64_t arg
)
1145 farg
.d
= float64_chs(farg
.d
);
1149 /* fctiw - fctiw. */
1150 uint64_t helper_fctiw (uint64_t arg
)
1155 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1156 /* sNaN conversion */
1157 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1158 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1159 /* qNan / infinity conversion */
1160 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1162 farg
.ll
= float64_to_int32(farg
.d
, &env
->fp_status
);
1163 #if USE_PRECISE_EMULATION
1164 /* XXX: higher bits are not supposed to be significant.
1165 * to make tests easier, return the same as a real PowerPC 750
1167 farg
.ll
|= 0xFFF80000ULL
<< 32;
1173 /* fctiwz - fctiwz. */
1174 uint64_t helper_fctiwz (uint64_t arg
)
1179 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1180 /* sNaN conversion */
1181 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1182 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1183 /* qNan / infinity conversion */
1184 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1186 farg
.ll
= float64_to_int32_round_to_zero(farg
.d
, &env
->fp_status
);
1187 #if USE_PRECISE_EMULATION
1188 /* XXX: higher bits are not supposed to be significant.
1189 * to make tests easier, return the same as a real PowerPC 750
1191 farg
.ll
|= 0xFFF80000ULL
<< 32;
1197 #if defined(TARGET_PPC64)
1198 /* fcfid - fcfid. */
1199 uint64_t helper_fcfid (uint64_t arg
)
1202 farg
.d
= int64_to_float64(arg
, &env
->fp_status
);
1206 /* fctid - fctid. */
1207 uint64_t helper_fctid (uint64_t arg
)
1212 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1213 /* sNaN conversion */
1214 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1215 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1216 /* qNan / infinity conversion */
1217 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1219 farg
.ll
= float64_to_int64(farg
.d
, &env
->fp_status
);
1224 /* fctidz - fctidz. */
1225 uint64_t helper_fctidz (uint64_t arg
)
1230 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1231 /* sNaN conversion */
1232 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1233 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1234 /* qNan / infinity conversion */
1235 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1237 farg
.ll
= float64_to_int64_round_to_zero(farg
.d
, &env
->fp_status
);
1244 static always_inline
uint64_t do_fri (uint64_t arg
, int rounding_mode
)
1249 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1251 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
| POWERPC_EXCP_FP_VXCVI
);
1252 } else if (unlikely(float64_is_nan(farg
.d
) || float64_is_infinity(farg
.d
))) {
1253 /* qNan / infinity round */
1254 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI
);
1256 set_float_rounding_mode(rounding_mode
, &env
->fp_status
);
1257 farg
.ll
= float64_round_to_int(farg
.d
, &env
->fp_status
);
1258 /* Restore rounding mode from FPSCR */
1259 fpscr_set_rounding_mode();
1264 uint64_t helper_frin (uint64_t arg
)
1266 return do_fri(arg
, float_round_nearest_even
);
1269 uint64_t helper_friz (uint64_t arg
)
1271 return do_fri(arg
, float_round_to_zero
);
1274 uint64_t helper_frip (uint64_t arg
)
1276 return do_fri(arg
, float_round_up
);
1279 uint64_t helper_frim (uint64_t arg
)
1281 return do_fri(arg
, float_round_down
);
1284 /* fmadd - fmadd. */
1285 uint64_t helper_fmadd (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1287 CPU_DoubleU farg1
, farg2
, farg3
;
1292 #if USE_PRECISE_EMULATION
1293 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1294 float64_is_signaling_nan(farg2
.d
) ||
1295 float64_is_signaling_nan(farg3
.d
))) {
1296 /* sNaN operation */
1297 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1298 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1299 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1300 /* Multiplication of zero by infinity */
1301 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1304 /* This is the way the PowerPC specification defines it */
1305 float128 ft0_128
, ft1_128
;
1307 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
1308 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
1309 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
1310 if (unlikely(float128_is_infinity(ft0_128
) && float64_is_infinity(farg3
.d
) &&
1311 float128_is_neg(ft0_128
) != float64_is_neg(farg3
.d
))) {
1312 /* Magnitude subtraction of infinities */
1313 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1315 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
1316 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
1317 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
1320 /* This is OK on x86 hosts */
1321 farg1
.d
= (farg1
.d
* farg2
.d
) + farg3
.d
;
1325 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1326 farg1
.d
= float64_add(farg1
.d
, farg3
.d
, &env
->fp_status
);
1331 /* fmsub - fmsub. */
1332 uint64_t helper_fmsub (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1334 CPU_DoubleU farg1
, farg2
, farg3
;
1339 #if USE_PRECISE_EMULATION
1340 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1341 float64_is_signaling_nan(farg2
.d
) ||
1342 float64_is_signaling_nan(farg3
.d
))) {
1343 /* sNaN operation */
1344 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1345 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1346 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1347 /* Multiplication of zero by infinity */
1348 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1351 /* This is the way the PowerPC specification defines it */
1352 float128 ft0_128
, ft1_128
;
1354 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
1355 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
1356 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
1357 if (unlikely(float128_is_infinity(ft0_128
) && float64_is_infinity(farg3
.d
) &&
1358 float128_is_neg(ft0_128
) == float64_is_neg(farg3
.d
))) {
1359 /* Magnitude subtraction of infinities */
1360 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1362 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
1363 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
1364 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
1367 /* This is OK on x86 hosts */
1368 farg1
.d
= (farg1
.d
* farg2
.d
) - farg3
.d
;
1372 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1373 farg1
.d
= float64_sub(farg1
.d
, farg3
.d
, &env
->fp_status
);
1378 /* fnmadd - fnmadd. */
1379 uint64_t helper_fnmadd (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1381 CPU_DoubleU farg1
, farg2
, farg3
;
1387 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1388 float64_is_signaling_nan(farg2
.d
) ||
1389 float64_is_signaling_nan(farg3
.d
))) {
1390 /* sNaN operation */
1391 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1392 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1393 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1394 /* Multiplication of zero by infinity */
1395 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1397 #if USE_PRECISE_EMULATION
1399 /* This is the way the PowerPC specification defines it */
1400 float128 ft0_128
, ft1_128
;
1402 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
1403 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
1404 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
1405 if (unlikely(float128_is_infinity(ft0_128
) && float64_is_infinity(farg3
.d
) &&
1406 float128_is_neg(ft0_128
) != float64_is_neg(farg3
.d
))) {
1407 /* Magnitude subtraction of infinities */
1408 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1410 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
1411 ft0_128
= float128_add(ft0_128
, ft1_128
, &env
->fp_status
);
1412 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
1415 /* This is OK on x86 hosts */
1416 farg1
.d
= (farg1
.d
* farg2
.d
) + farg3
.d
;
1419 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1420 farg1
.d
= float64_add(farg1
.d
, farg3
.d
, &env
->fp_status
);
1422 if (likely(!float64_is_nan(farg1
.d
)))
1423 farg1
.d
= float64_chs(farg1
.d
);
1428 /* fnmsub - fnmsub. */
1429 uint64_t helper_fnmsub (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1431 CPU_DoubleU farg1
, farg2
, farg3
;
1437 if (unlikely(float64_is_signaling_nan(farg1
.d
) ||
1438 float64_is_signaling_nan(farg2
.d
) ||
1439 float64_is_signaling_nan(farg3
.d
))) {
1440 /* sNaN operation */
1441 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1442 } else if (unlikely((float64_is_infinity(farg1
.d
) && float64_is_zero(farg2
.d
)) ||
1443 (float64_is_zero(farg1
.d
) && float64_is_infinity(farg2
.d
)))) {
1444 /* Multiplication of zero by infinity */
1445 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ
);
1447 #if USE_PRECISE_EMULATION
1449 /* This is the way the PowerPC specification defines it */
1450 float128 ft0_128
, ft1_128
;
1452 ft0_128
= float64_to_float128(farg1
.d
, &env
->fp_status
);
1453 ft1_128
= float64_to_float128(farg2
.d
, &env
->fp_status
);
1454 ft0_128
= float128_mul(ft0_128
, ft1_128
, &env
->fp_status
);
1455 if (unlikely(float128_is_infinity(ft0_128
) && float64_is_infinity(farg3
.d
) &&
1456 float128_is_neg(ft0_128
) == float64_is_neg(farg3
.d
))) {
1457 /* Magnitude subtraction of infinities */
1458 farg1
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI
);
1460 ft1_128
= float64_to_float128(farg3
.d
, &env
->fp_status
);
1461 ft0_128
= float128_sub(ft0_128
, ft1_128
, &env
->fp_status
);
1462 farg1
.d
= float128_to_float64(ft0_128
, &env
->fp_status
);
1465 /* This is OK on x86 hosts */
1466 farg1
.d
= (farg1
.d
* farg2
.d
) - farg3
.d
;
1469 farg1
.d
= float64_mul(farg1
.d
, farg2
.d
, &env
->fp_status
);
1470 farg1
.d
= float64_sub(farg1
.d
, farg3
.d
, &env
->fp_status
);
1472 if (likely(!float64_is_nan(farg1
.d
)))
1473 farg1
.d
= float64_chs(farg1
.d
);
1479 uint64_t helper_frsp (uint64_t arg
)
1485 #if USE_PRECISE_EMULATION
1486 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1487 /* sNaN square root */
1488 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1490 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
1491 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
1494 f32
= float64_to_float32(farg
.d
, &env
->fp_status
);
1495 farg
.d
= float32_to_float64(f32
, &env
->fp_status
);
1500 /* fsqrt - fsqrt. */
1501 uint64_t helper_fsqrt (uint64_t arg
)
1506 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1507 /* sNaN square root */
1508 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1509 } else if (unlikely(float64_is_neg(farg
.d
) && !float64_is_zero(farg
.d
))) {
1510 /* Square root of a negative nonzero number */
1511 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT
);
1513 farg
.d
= float64_sqrt(farg
.d
, &env
->fp_status
);
1519 uint64_t helper_fre (uint64_t arg
)
1521 CPU_DoubleU fone
, farg
;
1522 fone
.ll
= 0x3FF0000000000000ULL
; /* 1.0 */
1525 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1526 /* sNaN reciprocal */
1527 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1528 } else if (unlikely(float64_is_zero(farg
.d
))) {
1529 /* Zero reciprocal */
1530 farg
.ll
= float_zero_divide_excp(fone
.d
, farg
.d
);
1531 } else if (likely(isnormal(farg
.d
))) {
1532 farg
.d
= float64_div(fone
.d
, farg
.d
, &env
->fp_status
);
1534 if (farg
.ll
== 0x8000000000000000ULL
) {
1535 farg
.ll
= 0xFFF0000000000000ULL
;
1536 } else if (farg
.ll
== 0x0000000000000000ULL
) {
1537 farg
.ll
= 0x7FF0000000000000ULL
;
1538 } else if (float64_is_nan(farg
.d
)) {
1539 farg
.ll
= 0x7FF8000000000000ULL
;
1540 } else if (float64_is_neg(farg
.d
)) {
1541 farg
.ll
= 0x8000000000000000ULL
;
1543 farg
.ll
= 0x0000000000000000ULL
;
1550 uint64_t helper_fres (uint64_t arg
)
1552 CPU_DoubleU fone
, farg
;
1553 fone
.ll
= 0x3FF0000000000000ULL
; /* 1.0 */
1556 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1557 /* sNaN reciprocal */
1558 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1559 } else if (unlikely(float64_is_zero(farg
.d
))) {
1560 /* Zero reciprocal */
1561 farg
.ll
= float_zero_divide_excp(fone
.d
, farg
.d
);
1562 } else if (likely(isnormal(farg
.d
))) {
1563 #if USE_PRECISE_EMULATION
1564 farg
.d
= float64_div(fone
.d
, farg
.d
, &env
->fp_status
);
1565 farg
.d
= float64_to_float32(farg
.d
, &env
->fp_status
);
1567 farg
.d
= float32_div(fone
.d
, farg
.d
, &env
->fp_status
);
1570 if (farg
.ll
== 0x8000000000000000ULL
) {
1571 farg
.ll
= 0xFFF0000000000000ULL
;
1572 } else if (farg
.ll
== 0x0000000000000000ULL
) {
1573 farg
.ll
= 0x7FF0000000000000ULL
;
1574 } else if (float64_is_nan(farg
.d
)) {
1575 farg
.ll
= 0x7FF8000000000000ULL
;
1576 } else if (float64_is_neg(farg
.d
)) {
1577 farg
.ll
= 0x8000000000000000ULL
;
1579 farg
.ll
= 0x0000000000000000ULL
;
1585 /* frsqrte - frsqrte. */
1586 uint64_t helper_frsqrte (uint64_t arg
)
1588 CPU_DoubleU fone
, farg
;
1589 fone
.ll
= 0x3FF0000000000000ULL
; /* 1.0 */
1592 if (unlikely(float64_is_signaling_nan(farg
.d
))) {
1593 /* sNaN reciprocal square root */
1594 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1595 } else if (unlikely(float64_is_neg(farg
.d
) && !float64_is_zero(farg
.d
))) {
1596 /* Reciprocal square root of a negative nonzero number */
1597 farg
.ll
= fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT
);
1598 } else if (likely(isnormal(farg
.d
))) {
1599 farg
.d
= float64_sqrt(farg
.d
, &env
->fp_status
);
1600 farg
.d
= float32_div(fone
.d
, farg
.d
, &env
->fp_status
);
1602 if (farg
.ll
== 0x8000000000000000ULL
) {
1603 farg
.ll
= 0xFFF0000000000000ULL
;
1604 } else if (farg
.ll
== 0x0000000000000000ULL
) {
1605 farg
.ll
= 0x7FF0000000000000ULL
;
1606 } else if (float64_is_nan(farg
.d
)) {
1607 farg
.ll
|= 0x000FFFFFFFFFFFFFULL
;
1608 } else if (float64_is_neg(farg
.d
)) {
1609 farg
.ll
= 0x7FF8000000000000ULL
;
1611 farg
.ll
= 0x0000000000000000ULL
;
1618 uint64_t helper_fsel (uint64_t arg1
, uint64_t arg2
, uint64_t arg3
)
1624 if (!float64_is_neg(farg1
.d
) || float64_is_zero(farg1
.d
))
1630 void helper_fcmpu (uint64_t arg1
, uint64_t arg2
, uint32_t crfD
)
1632 CPU_DoubleU farg1
, farg2
;
1637 if (unlikely(float64_is_nan(farg1
.d
) ||
1638 float64_is_nan(farg2
.d
))) {
1640 } else if (float64_lt(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1642 } else if (!float64_le(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1648 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1649 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1650 env
->crf
[crfD
] = ret
;
1651 if (unlikely(ret
== 0x01UL
1652 && (float64_is_signaling_nan(farg1
.d
) ||
1653 float64_is_signaling_nan(farg2
.d
)))) {
1654 /* sNaN comparison */
1655 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
);
1659 void helper_fcmpo (uint64_t arg1
, uint64_t arg2
, uint32_t crfD
)
1661 CPU_DoubleU farg1
, farg2
;
1666 if (unlikely(float64_is_nan(farg1
.d
) ||
1667 float64_is_nan(farg2
.d
))) {
1669 } else if (float64_lt(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1671 } else if (!float64_le(farg1
.d
, farg2
.d
, &env
->fp_status
)) {
1677 env
->fpscr
&= ~(0x0F << FPSCR_FPRF
);
1678 env
->fpscr
|= ret
<< FPSCR_FPRF
;
1679 env
->crf
[crfD
] = ret
;
1680 if (unlikely (ret
== 0x01UL
)) {
1681 if (float64_is_signaling_nan(farg1
.d
) ||
1682 float64_is_signaling_nan(farg2
.d
)) {
1683 /* sNaN comparison */
1684 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN
|
1685 POWERPC_EXCP_FP_VXVC
);
1687 /* qNaN comparison */
1688 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC
);
1693 #if !defined (CONFIG_USER_ONLY)
1694 void helper_store_msr (target_ulong val
)
1696 val
= hreg_store_msr(env
, val
, 0);
1698 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1699 helper_raise_exception(val
);
1703 static always_inline
void do_rfi (target_ulong nip
, target_ulong msr
,
1704 target_ulong msrm
, int keep_msrh
)
1706 #if defined(TARGET_PPC64)
1707 if (msr
& (1ULL << MSR_SF
)) {
1708 nip
= (uint64_t)nip
;
1709 msr
&= (uint64_t)msrm
;
1711 nip
= (uint32_t)nip
;
1712 msr
= (uint32_t)(msr
& msrm
);
1714 msr
|= env
->msr
& ~((uint64_t)0xFFFFFFFF);
1717 nip
= (uint32_t)nip
;
1718 msr
&= (uint32_t)msrm
;
1720 /* XXX: beware: this is false if VLE is supported */
1721 env
->nip
= nip
& ~((target_ulong
)0x00000003);
1722 hreg_store_msr(env
, msr
, 1);
1723 #if defined (DEBUG_OP)
1724 cpu_dump_rfi(env
->nip
, env
->msr
);
1726 /* No need to raise an exception here,
1727 * as rfi is always the last insn of a TB
1729 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1732 void helper_rfi (void)
1734 do_rfi(env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
1735 ~((target_ulong
)0xFFFF0000), 1);
1738 #if defined(TARGET_PPC64)
1739 void helper_rfid (void)
1741 do_rfi(env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
1742 ~((target_ulong
)0xFFFF0000), 0);
1745 void helper_hrfid (void)
1747 do_rfi(env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
],
1748 ~((target_ulong
)0xFFFF0000), 0);
1753 void helper_tw (target_ulong arg1
, target_ulong arg2
, uint32_t flags
)
1755 if (!likely(!(((int32_t)arg1
< (int32_t)arg2
&& (flags
& 0x10)) ||
1756 ((int32_t)arg1
> (int32_t)arg2
&& (flags
& 0x08)) ||
1757 ((int32_t)arg1
== (int32_t)arg2
&& (flags
& 0x04)) ||
1758 ((uint32_t)arg1
< (uint32_t)arg2
&& (flags
& 0x02)) ||
1759 ((uint32_t)arg1
> (uint32_t)arg2
&& (flags
& 0x01))))) {
1760 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
1764 #if defined(TARGET_PPC64)
1765 void helper_td (target_ulong arg1
, target_ulong arg2
, uint32_t flags
)
1767 if (!likely(!(((int64_t)arg1
< (int64_t)arg2
&& (flags
& 0x10)) ||
1768 ((int64_t)arg1
> (int64_t)arg2
&& (flags
& 0x08)) ||
1769 ((int64_t)arg1
== (int64_t)arg2
&& (flags
& 0x04)) ||
1770 ((uint64_t)arg1
< (uint64_t)arg2
&& (flags
& 0x02)) ||
1771 ((uint64_t)arg1
> (uint64_t)arg2
&& (flags
& 0x01)))))
1772 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
1776 /*****************************************************************************/
1777 /* PowerPC 601 specific instructions (POWER bridge) */
1779 target_ulong
helper_clcs (uint32_t arg
)
1783 /* Instruction cache line size */
1784 return env
->icache_line_size
;
1787 /* Data cache line size */
1788 return env
->dcache_line_size
;
1791 /* Minimum cache line size */
1792 return (env
->icache_line_size
< env
->dcache_line_size
) ?
1793 env
->icache_line_size
: env
->dcache_line_size
;
1796 /* Maximum cache line size */
1797 return (env
->icache_line_size
> env
->dcache_line_size
) ?
1798 env
->icache_line_size
: env
->dcache_line_size
;
1807 target_ulong
helper_div (target_ulong arg1
, target_ulong arg2
)
1809 uint64_t tmp
= (uint64_t)arg1
<< 32 | env
->spr
[SPR_MQ
];
1811 if (((int32_t)tmp
== INT32_MIN
&& (int32_t)arg2
== (int32_t)-1) ||
1812 (int32_t)arg2
== 0) {
1813 env
->spr
[SPR_MQ
] = 0;
1816 env
->spr
[SPR_MQ
] = tmp
% arg2
;
1817 return tmp
/ (int32_t)arg2
;
1821 target_ulong
helper_divo (target_ulong arg1
, target_ulong arg2
)
1823 uint64_t tmp
= (uint64_t)arg1
<< 32 | env
->spr
[SPR_MQ
];
1825 if (((int32_t)tmp
== INT32_MIN
&& (int32_t)arg2
== (int32_t)-1) ||
1826 (int32_t)arg2
== 0) {
1827 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1828 env
->spr
[SPR_MQ
] = 0;
1831 env
->spr
[SPR_MQ
] = tmp
% arg2
;
1832 tmp
/= (int32_t)arg2
;
1833 if ((int32_t)tmp
!= tmp
) {
1834 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1836 env
->xer
&= ~(1 << XER_OV
);
1842 target_ulong
helper_divs (target_ulong arg1
, target_ulong arg2
)
1844 if (((int32_t)arg1
== INT32_MIN
&& (int32_t)arg2
== (int32_t)-1) ||
1845 (int32_t)arg2
== 0) {
1846 env
->spr
[SPR_MQ
] = 0;
1849 env
->spr
[SPR_MQ
] = (int32_t)arg1
% (int32_t)arg2
;
1850 return (int32_t)arg1
/ (int32_t)arg2
;
1854 target_ulong
helper_divso (target_ulong arg1
, target_ulong arg2
)
1856 if (((int32_t)arg1
== INT32_MIN
&& (int32_t)arg2
== (int32_t)-1) ||
1857 (int32_t)arg2
== 0) {
1858 env
->xer
|= (1 << XER_OV
) | (1 << XER_SO
);
1859 env
->spr
[SPR_MQ
] = 0;
1862 env
->xer
&= ~(1 << XER_OV
);
1863 env
->spr
[SPR_MQ
] = (int32_t)arg1
% (int32_t)arg2
;
1864 return (int32_t)arg1
/ (int32_t)arg2
;
1868 #if !defined (CONFIG_USER_ONLY)
1869 target_ulong
helper_rac (target_ulong addr
)
1873 target_ulong ret
= 0;
1875 /* We don't have to generate many instances of this instruction,
1876 * as rac is supervisor only.
1878 /* XXX: FIX THIS: Pretend we have no BAT */
1879 nb_BATs
= env
->nb_BATs
;
1881 if (get_physical_address(env
, &ctx
, addr
, 0, ACCESS_INT
) == 0)
1883 env
->nb_BATs
= nb_BATs
;
1887 void helper_rfsvc (void)
1889 do_rfi(env
->lr
, env
->ctr
, 0x0000FFFF, 0);
1893 /*****************************************************************************/
1894 /* 602 specific instructions */
1895 /* mfrom is the most crazy instruction ever seen, imho ! */
1896 /* Real implementation uses a ROM table. Do the same */
1897 /* Extremly decomposed:
1899 * return 256 * log10(10 + 1.0) + 0.5
1901 #if !defined (CONFIG_USER_ONLY)
1902 target_ulong
helper_602_mfrom (target_ulong arg
)
1904 if (likely(arg
< 602)) {
1905 #include "mfrom_table.c"
1906 return mfrom_ROM_table
[arg
];
1913 /*****************************************************************************/
1914 /* Embedded PowerPC specific helpers */
1916 /* XXX: to be improved to check access rights when in user-mode */
1917 target_ulong
helper_load_dcr (target_ulong dcrn
)
1919 target_ulong val
= 0;
1921 if (unlikely(env
->dcr_env
== NULL
)) {
1922 if (loglevel
!= 0) {
1923 fprintf(logfile
, "No DCR environment\n");
1925 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1926 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
1927 } else if (unlikely(ppc_dcr_read(env
->dcr_env
, dcrn
, &val
) != 0)) {
1928 if (loglevel
!= 0) {
1929 fprintf(logfile
, "DCR read error %d %03x\n", (int)dcrn
, (int)dcrn
);
1931 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1932 POWERPC_EXCP_INVAL
| POWERPC_EXCP_PRIV_REG
);
1937 void helper_store_dcr (target_ulong dcrn
, target_ulong val
)
1939 if (unlikely(env
->dcr_env
== NULL
)) {
1940 if (loglevel
!= 0) {
1941 fprintf(logfile
, "No DCR environment\n");
1943 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1944 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
1945 } else if (unlikely(ppc_dcr_write(env
->dcr_env
, dcrn
, val
) != 0)) {
1946 if (loglevel
!= 0) {
1947 fprintf(logfile
, "DCR write error %d %03x\n", (int)dcrn
, (int)dcrn
);
1949 helper_raise_exception_err(POWERPC_EXCP_PROGRAM
,
1950 POWERPC_EXCP_INVAL
| POWERPC_EXCP_PRIV_REG
);
1954 #if !defined(CONFIG_USER_ONLY)
1955 void helper_40x_rfci (void)
1957 do_rfi(env
->spr
[SPR_40x_SRR2
], env
->spr
[SPR_40x_SRR3
],
1958 ~((target_ulong
)0xFFFF0000), 0);
1961 void helper_rfci (void)
1963 do_rfi(env
->spr
[SPR_BOOKE_CSRR0
], SPR_BOOKE_CSRR1
,
1964 ~((target_ulong
)0x3FFF0000), 0);
1967 void helper_rfdi (void)
1969 do_rfi(env
->spr
[SPR_BOOKE_DSRR0
], SPR_BOOKE_DSRR1
,
1970 ~((target_ulong
)0x3FFF0000), 0);
1973 void helper_rfmci (void)
1975 do_rfi(env
->spr
[SPR_BOOKE_MCSRR0
], SPR_BOOKE_MCSRR1
,
1976 ~((target_ulong
)0x3FFF0000), 0);
1981 target_ulong
helper_dlmzb (target_ulong high
, target_ulong low
, uint32_t update_Rc
)
1987 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1988 if ((high
& mask
) == 0) {
1996 for (mask
= 0xFF000000; mask
!= 0; mask
= mask
>> 8) {
1997 if ((low
& mask
) == 0) {
2009 env
->xer
= (env
->xer
& ~0x7F) | i
;
2011 env
->crf
[0] |= xer_so
;
2016 /*****************************************************************************/
2017 /* SPE extension helpers */
2018 /* Use a table to make this quicker */
2019 static uint8_t hbrev
[16] = {
2020 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2021 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2024 static always_inline
uint8_t byte_reverse (uint8_t val
)
2026 return hbrev
[val
>> 4] | (hbrev
[val
& 0xF] << 4);
2029 static always_inline
uint32_t word_reverse (uint32_t val
)
2031 return byte_reverse(val
>> 24) | (byte_reverse(val
>> 16) << 8) |
2032 (byte_reverse(val
>> 8) << 16) | (byte_reverse(val
) << 24);
2035 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2036 target_ulong
helper_brinc (target_ulong arg1
, target_ulong arg2
)
2038 uint32_t a
, b
, d
, mask
;
2040 mask
= UINT32_MAX
>> (32 - MASKBITS
);
2043 d
= word_reverse(1 + word_reverse(a
| ~b
));
2044 return (arg1
& ~mask
) | (d
& b
);
2047 uint32_t helper_cntlsw32 (uint32_t val
)
2049 if (val
& 0x80000000)
2055 uint32_t helper_cntlzw32 (uint32_t val
)
2060 /* Single-precision floating-point conversions */
2061 static always_inline
uint32_t efscfsi (uint32_t val
)
2065 u
.f
= int32_to_float32(val
, &env
->spe_status
);
2070 static always_inline
uint32_t efscfui (uint32_t val
)
2074 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
2079 static always_inline
int32_t efsctsi (uint32_t val
)
2084 /* NaN are not treated the same way IEEE 754 does */
2085 if (unlikely(float32_is_nan(u
.f
)))
2088 return float32_to_int32(u
.f
, &env
->spe_status
);
2091 static always_inline
uint32_t efsctui (uint32_t val
)
2096 /* NaN are not treated the same way IEEE 754 does */
2097 if (unlikely(float32_is_nan(u
.f
)))
2100 return float32_to_uint32(u
.f
, &env
->spe_status
);
2103 static always_inline
uint32_t efsctsiz (uint32_t val
)
2108 /* NaN are not treated the same way IEEE 754 does */
2109 if (unlikely(float32_is_nan(u
.f
)))
2112 return float32_to_int32_round_to_zero(u
.f
, &env
->spe_status
);
2115 static always_inline
uint32_t efsctuiz (uint32_t val
)
2120 /* NaN are not treated the same way IEEE 754 does */
2121 if (unlikely(float32_is_nan(u
.f
)))
2124 return float32_to_uint32_round_to_zero(u
.f
, &env
->spe_status
);
2127 static always_inline
uint32_t efscfsf (uint32_t val
)
2132 u
.f
= int32_to_float32(val
, &env
->spe_status
);
2133 tmp
= int64_to_float32(1ULL << 32, &env
->spe_status
);
2134 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
2139 static always_inline
uint32_t efscfuf (uint32_t val
)
2144 u
.f
= uint32_to_float32(val
, &env
->spe_status
);
2145 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
2146 u
.f
= float32_div(u
.f
, tmp
, &env
->spe_status
);
2151 static always_inline
uint32_t efsctsf (uint32_t val
)
2157 /* NaN are not treated the same way IEEE 754 does */
2158 if (unlikely(float32_is_nan(u
.f
)))
2160 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
2161 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
2163 return float32_to_int32(u
.f
, &env
->spe_status
);
2166 static always_inline
uint32_t efsctuf (uint32_t val
)
2172 /* NaN are not treated the same way IEEE 754 does */
2173 if (unlikely(float32_is_nan(u
.f
)))
2175 tmp
= uint64_to_float32(1ULL << 32, &env
->spe_status
);
2176 u
.f
= float32_mul(u
.f
, tmp
, &env
->spe_status
);
2178 return float32_to_uint32(u
.f
, &env
->spe_status
);
2181 #define HELPER_SPE_SINGLE_CONV(name) \
2182 uint32_t helper_e##name (uint32_t val) \
2184 return e##name(val); \
2187 HELPER_SPE_SINGLE_CONV(fscfsi
);
2189 HELPER_SPE_SINGLE_CONV(fscfui
);
2191 HELPER_SPE_SINGLE_CONV(fscfuf
);
2193 HELPER_SPE_SINGLE_CONV(fscfsf
);
2195 HELPER_SPE_SINGLE_CONV(fsctsi
);
2197 HELPER_SPE_SINGLE_CONV(fsctui
);
2199 HELPER_SPE_SINGLE_CONV(fsctsiz
);
2201 HELPER_SPE_SINGLE_CONV(fsctuiz
);
2203 HELPER_SPE_SINGLE_CONV(fsctsf
);
2205 HELPER_SPE_SINGLE_CONV(fsctuf
);
2207 #define HELPER_SPE_VECTOR_CONV(name) \
2208 uint64_t helper_ev##name (uint64_t val) \
2210 return ((uint64_t)e##name(val >> 32) << 32) | \
2211 (uint64_t)e##name(val); \
2214 HELPER_SPE_VECTOR_CONV(fscfsi
);
2216 HELPER_SPE_VECTOR_CONV(fscfui
);
2218 HELPER_SPE_VECTOR_CONV(fscfuf
);
2220 HELPER_SPE_VECTOR_CONV(fscfsf
);
2222 HELPER_SPE_VECTOR_CONV(fsctsi
);
2224 HELPER_SPE_VECTOR_CONV(fsctui
);
2226 HELPER_SPE_VECTOR_CONV(fsctsiz
);
2228 HELPER_SPE_VECTOR_CONV(fsctuiz
);
2230 HELPER_SPE_VECTOR_CONV(fsctsf
);
2232 HELPER_SPE_VECTOR_CONV(fsctuf
);
2234 /* Single-precision floating-point arithmetic */
2235 static always_inline
uint32_t efsadd (uint32_t op1
, uint32_t op2
)
2240 u1
.f
= float32_add(u1
.f
, u2
.f
, &env
->spe_status
);
2244 static always_inline
uint32_t efssub (uint32_t op1
, uint32_t op2
)
2249 u1
.f
= float32_sub(u1
.f
, u2
.f
, &env
->spe_status
);
2253 static always_inline
uint32_t efsmul (uint32_t op1
, uint32_t op2
)
2258 u1
.f
= float32_mul(u1
.f
, u2
.f
, &env
->spe_status
);
2262 static always_inline
uint32_t efsdiv (uint32_t op1
, uint32_t op2
)
2267 u1
.f
= float32_div(u1
.f
, u2
.f
, &env
->spe_status
);
2271 #define HELPER_SPE_SINGLE_ARITH(name) \
2272 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2274 return e##name(op1, op2); \
2277 HELPER_SPE_SINGLE_ARITH(fsadd
);
2279 HELPER_SPE_SINGLE_ARITH(fssub
);
2281 HELPER_SPE_SINGLE_ARITH(fsmul
);
2283 HELPER_SPE_SINGLE_ARITH(fsdiv
);
2285 #define HELPER_SPE_VECTOR_ARITH(name) \
2286 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2288 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2289 (uint64_t)e##name(op1, op2); \
2292 HELPER_SPE_VECTOR_ARITH(fsadd
);
2294 HELPER_SPE_VECTOR_ARITH(fssub
);
2296 HELPER_SPE_VECTOR_ARITH(fsmul
);
2298 HELPER_SPE_VECTOR_ARITH(fsdiv
);
2300 /* Single-precision floating-point comparisons */
2301 static always_inline
uint32_t efststlt (uint32_t op1
, uint32_t op2
)
2306 return float32_lt(u1
.f
, u2
.f
, &env
->spe_status
) ? 4 : 0;
2309 static always_inline
uint32_t efststgt (uint32_t op1
, uint32_t op2
)
2314 return float32_le(u1
.f
, u2
.f
, &env
->spe_status
) ? 0 : 4;
2317 static always_inline
uint32_t efststeq (uint32_t op1
, uint32_t op2
)
2322 return float32_eq(u1
.f
, u2
.f
, &env
->spe_status
) ? 4 : 0;
2325 static always_inline
uint32_t efscmplt (uint32_t op1
, uint32_t op2
)
2327 /* XXX: TODO: test special values (NaN, infinites, ...) */
2328 return efststlt(op1
, op2
);
2331 static always_inline
uint32_t efscmpgt (uint32_t op1
, uint32_t op2
)
2333 /* XXX: TODO: test special values (NaN, infinites, ...) */
2334 return efststgt(op1
, op2
);
2337 static always_inline
uint32_t efscmpeq (uint32_t op1
, uint32_t op2
)
2339 /* XXX: TODO: test special values (NaN, infinites, ...) */
2340 return efststeq(op1
, op2
);
2343 #define HELPER_SINGLE_SPE_CMP(name) \
2344 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2346 return e##name(op1, op2) << 2; \
2349 HELPER_SINGLE_SPE_CMP(fststlt
);
2351 HELPER_SINGLE_SPE_CMP(fststgt
);
2353 HELPER_SINGLE_SPE_CMP(fststeq
);
2355 HELPER_SINGLE_SPE_CMP(fscmplt
);
2357 HELPER_SINGLE_SPE_CMP(fscmpgt
);
2359 HELPER_SINGLE_SPE_CMP(fscmpeq
);
2361 static always_inline
uint32_t evcmp_merge (int t0
, int t1
)
2363 return (t0
<< 3) | (t1
<< 2) | ((t0
| t1
) << 1) | (t0
& t1
);
2366 #define HELPER_VECTOR_SPE_CMP(name) \
2367 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2369 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2372 HELPER_VECTOR_SPE_CMP(fststlt
);
2374 HELPER_VECTOR_SPE_CMP(fststgt
);
2376 HELPER_VECTOR_SPE_CMP(fststeq
);
2378 HELPER_VECTOR_SPE_CMP(fscmplt
);
2380 HELPER_VECTOR_SPE_CMP(fscmpgt
);
2382 HELPER_VECTOR_SPE_CMP(fscmpeq
);
2384 /* Double-precision floating-point conversion */
2385 uint64_t helper_efdcfsi (uint32_t val
)
2389 u
.d
= int32_to_float64(val
, &env
->spe_status
);
2394 uint64_t helper_efdcfsid (uint64_t val
)
2398 u
.d
= int64_to_float64(val
, &env
->spe_status
);
2403 uint64_t helper_efdcfui (uint32_t val
)
2407 u
.d
= uint32_to_float64(val
, &env
->spe_status
);
2412 uint64_t helper_efdcfuid (uint64_t val
)
2416 u
.d
= uint64_to_float64(val
, &env
->spe_status
);
2421 uint32_t helper_efdctsi (uint64_t val
)
2426 /* NaN are not treated the same way IEEE 754 does */
2427 if (unlikely(float64_is_nan(u
.d
)))
2430 return float64_to_int32(u
.d
, &env
->spe_status
);
2433 uint32_t helper_efdctui (uint64_t val
)
2438 /* NaN are not treated the same way IEEE 754 does */
2439 if (unlikely(float64_is_nan(u
.d
)))
2442 return float64_to_uint32(u
.d
, &env
->spe_status
);
2445 uint32_t helper_efdctsiz (uint64_t val
)
2450 /* NaN are not treated the same way IEEE 754 does */
2451 if (unlikely(float64_is_nan(u
.d
)))
2454 return float64_to_int32_round_to_zero(u
.d
, &env
->spe_status
);
2457 uint64_t helper_efdctsidz (uint64_t val
)
2462 /* NaN are not treated the same way IEEE 754 does */
2463 if (unlikely(float64_is_nan(u
.d
)))
2466 return float64_to_int64_round_to_zero(u
.d
, &env
->spe_status
);
2469 uint32_t helper_efdctuiz (uint64_t val
)
2474 /* NaN are not treated the same way IEEE 754 does */
2475 if (unlikely(float64_is_nan(u
.d
)))
2478 return float64_to_uint32_round_to_zero(u
.d
, &env
->spe_status
);
2481 uint64_t helper_efdctuidz (uint64_t val
)
2486 /* NaN are not treated the same way IEEE 754 does */
2487 if (unlikely(float64_is_nan(u
.d
)))
2490 return float64_to_uint64_round_to_zero(u
.d
, &env
->spe_status
);
2493 uint64_t helper_efdcfsf (uint32_t val
)
2498 u
.d
= int32_to_float64(val
, &env
->spe_status
);
2499 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
2500 u
.d
= float64_div(u
.d
, tmp
, &env
->spe_status
);
2505 uint64_t helper_efdcfuf (uint32_t val
)
2510 u
.d
= uint32_to_float64(val
, &env
->spe_status
);
2511 tmp
= int64_to_float64(1ULL << 32, &env
->spe_status
);
2512 u
.d
= float64_div(u
.d
, tmp
, &env
->spe_status
);
2517 uint32_t helper_efdctsf (uint64_t val
)
2523 /* NaN are not treated the same way IEEE 754 does */
2524 if (unlikely(float64_is_nan(u
.d
)))
2526 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2527 u
.d
= float64_mul(u
.d
, tmp
, &env
->spe_status
);
2529 return float64_to_int32(u
.d
, &env
->spe_status
);
2532 uint32_t helper_efdctuf (uint64_t val
)
2538 /* NaN are not treated the same way IEEE 754 does */
2539 if (unlikely(float64_is_nan(u
.d
)))
2541 tmp
= uint64_to_float64(1ULL << 32, &env
->spe_status
);
2542 u
.d
= float64_mul(u
.d
, tmp
, &env
->spe_status
);
2544 return float64_to_uint32(u
.d
, &env
->spe_status
);
2547 uint32_t helper_efscfd (uint64_t val
)
2553 u2
.f
= float64_to_float32(u1
.d
, &env
->spe_status
);
2558 uint64_t helper_efdcfs (uint32_t val
)
2564 u2
.d
= float32_to_float64(u1
.f
, &env
->spe_status
);
2569 /* Double precision fixed-point arithmetic */
2570 uint64_t helper_efdadd (uint64_t op1
, uint64_t op2
)
2575 u1
.d
= float64_add(u1
.d
, u2
.d
, &env
->spe_status
);
2579 uint64_t helper_efdsub (uint64_t op1
, uint64_t op2
)
2584 u1
.d
= float64_sub(u1
.d
, u2
.d
, &env
->spe_status
);
2588 uint64_t helper_efdmul (uint64_t op1
, uint64_t op2
)
2593 u1
.d
= float64_mul(u1
.d
, u2
.d
, &env
->spe_status
);
2597 uint64_t helper_efddiv (uint64_t op1
, uint64_t op2
)
2602 u1
.d
= float64_div(u1
.d
, u2
.d
, &env
->spe_status
);
2606 /* Double precision floating point helpers */
2607 uint32_t helper_efdtstlt (uint64_t op1
, uint64_t op2
)
2612 return float64_lt(u1
.d
, u2
.d
, &env
->spe_status
) ? 4 : 0;
2615 uint32_t helper_efdtstgt (uint64_t op1
, uint64_t op2
)
2620 return float64_le(u1
.d
, u2
.d
, &env
->spe_status
) ? 0 : 4;
2623 uint32_t helper_efdtsteq (uint64_t op1
, uint64_t op2
)
2628 return float64_eq(u1
.d
, u2
.d
, &env
->spe_status
) ? 4 : 0;
2631 uint32_t helper_efdcmplt (uint64_t op1
, uint64_t op2
)
2633 /* XXX: TODO: test special values (NaN, infinites, ...) */
2634 return helper_efdtstlt(op1
, op2
);
2637 uint32_t helper_efdcmpgt (uint64_t op1
, uint64_t op2
)
2639 /* XXX: TODO: test special values (NaN, infinites, ...) */
2640 return helper_efdtstgt(op1
, op2
);
2643 uint32_t helper_efdcmpeq (uint64_t op1
, uint64_t op2
)
2645 /* XXX: TODO: test special values (NaN, infinites, ...) */
2646 return helper_efdtsteq(op1
, op2
);
2649 /*****************************************************************************/
2650 /* Softmmu support */
2651 #if !defined (CONFIG_USER_ONLY)
2653 #define MMUSUFFIX _mmu
2656 #include "softmmu_template.h"
2659 #include "softmmu_template.h"
2662 #include "softmmu_template.h"
2665 #include "softmmu_template.h"
2667 /* try to fill the TLB and return an exception if error. If retaddr is
2668 NULL, it means that the function was called in C code (i.e. not
2669 from generated code or from helper.c) */
2670 /* XXX: fix it to restore all registers */
2671 void tlb_fill (target_ulong addr
, int is_write
, int mmu_idx
, void *retaddr
)
2673 TranslationBlock
*tb
;
2674 CPUState
*saved_env
;
2678 /* XXX: hack to restore env in all cases, even if not called from
2681 env
= cpu_single_env
;
2682 ret
= cpu_ppc_handle_mmu_fault(env
, addr
, is_write
, mmu_idx
, 1);
2683 if (unlikely(ret
!= 0)) {
2684 if (likely(retaddr
)) {
2685 /* now we have a real cpu fault */
2686 pc
= (unsigned long)retaddr
;
2687 tb
= tb_find_pc(pc
);
2689 /* the PC is inside the translated code. It means that we have
2690 a virtual CPU fault */
2691 cpu_restore_state(tb
, env
, pc
, NULL
);
2694 helper_raise_exception_err(env
->exception_index
, env
->error_code
);
2699 /* Segment registers load and store */
2700 target_ulong
helper_load_sr (target_ulong sr_num
)
2702 return env
->sr
[sr_num
];
2705 void helper_store_sr (target_ulong sr_num
, target_ulong val
)
2707 ppc_store_sr(env
, sr_num
, val
);
2710 /* SLB management */
2711 #if defined(TARGET_PPC64)
2712 target_ulong
helper_load_slb (target_ulong slb_nr
)
2714 return ppc_load_slb(env
, slb_nr
);
2717 void helper_store_slb (target_ulong slb_nr
, target_ulong rs
)
2719 ppc_store_slb(env
, slb_nr
, rs
);
2722 void helper_slbia (void)
2724 ppc_slb_invalidate_all(env
);
2727 void helper_slbie (target_ulong addr
)
2729 ppc_slb_invalidate_one(env
, addr
);
2732 #endif /* defined(TARGET_PPC64) */
2734 /* TLB management */
2735 void helper_tlbia (void)
2737 ppc_tlb_invalidate_all(env
);
2740 void helper_tlbie (target_ulong addr
)
2742 ppc_tlb_invalidate_one(env
, addr
);
2745 /* Software driven TLBs management */
2746 /* PowerPC 602/603 software TLB load instructions helpers */
2747 static void do_6xx_tlb (target_ulong new_EPN
, int is_code
)
2749 target_ulong RPN
, CMP
, EPN
;
2752 RPN
= env
->spr
[SPR_RPA
];
2754 CMP
= env
->spr
[SPR_ICMP
];
2755 EPN
= env
->spr
[SPR_IMISS
];
2757 CMP
= env
->spr
[SPR_DCMP
];
2758 EPN
= env
->spr
[SPR_DMISS
];
2760 way
= (env
->spr
[SPR_SRR1
] >> 17) & 1;
2761 #if defined (DEBUG_SOFTWARE_TLB)
2762 if (loglevel
!= 0) {
2763 fprintf(logfile
, "%s: EPN " ADDRX
" " ADDRX
" PTE0 " ADDRX
2764 " PTE1 " ADDRX
" way %d\n",
2765 __func__
, new_EPN
, EPN
, CMP
, RPN
, way
);
2768 /* Store this TLB */
2769 ppc6xx_tlb_store(env
, (uint32_t)(new_EPN
& TARGET_PAGE_MASK
),
2770 way
, is_code
, CMP
, RPN
);
2773 void helper_6xx_tlbd (target_ulong EPN
)
2778 void helper_6xx_tlbi (target_ulong EPN
)
2783 /* PowerPC 74xx software TLB load instructions helpers */
2784 static void do_74xx_tlb (target_ulong new_EPN
, int is_code
)
2786 target_ulong RPN
, CMP
, EPN
;
2789 RPN
= env
->spr
[SPR_PTELO
];
2790 CMP
= env
->spr
[SPR_PTEHI
];
2791 EPN
= env
->spr
[SPR_TLBMISS
] & ~0x3;
2792 way
= env
->spr
[SPR_TLBMISS
] & 0x3;
2793 #if defined (DEBUG_SOFTWARE_TLB)
2794 if (loglevel
!= 0) {
2795 fprintf(logfile
, "%s: EPN " ADDRX
" " ADDRX
" PTE0 " ADDRX
2796 " PTE1 " ADDRX
" way %d\n",
2797 __func__
, new_EPN
, EPN
, CMP
, RPN
, way
);
2800 /* Store this TLB */
2801 ppc6xx_tlb_store(env
, (uint32_t)(new_EPN
& TARGET_PAGE_MASK
),
2802 way
, is_code
, CMP
, RPN
);
2805 void helper_74xx_tlbd (target_ulong EPN
)
2807 do_74xx_tlb(EPN
, 0);
2810 void helper_74xx_tlbi (target_ulong EPN
)
2812 do_74xx_tlb(EPN
, 1);
2815 static always_inline target_ulong
booke_tlb_to_page_size (int size
)
2817 return 1024 << (2 * size
);
2820 static always_inline
int booke_page_size_to_tlb (target_ulong page_size
)
2824 switch (page_size
) {
2858 #if defined (TARGET_PPC64)
2859 case 0x000100000000ULL
:
2862 case 0x000400000000ULL
:
2865 case 0x001000000000ULL
:
2868 case 0x004000000000ULL
:
2871 case 0x010000000000ULL
:
2883 /* Helpers for 4xx TLB management */
2884 target_ulong
helper_4xx_tlbre_lo (target_ulong entry
)
2891 tlb
= &env
->tlb
[entry
].tlbe
;
2893 if (tlb
->prot
& PAGE_VALID
)
2895 size
= booke_page_size_to_tlb(tlb
->size
);
2896 if (size
< 0 || size
> 0x7)
2899 env
->spr
[SPR_40x_PID
] = tlb
->PID
;
2903 target_ulong
helper_4xx_tlbre_hi (target_ulong entry
)
2909 tlb
= &env
->tlb
[entry
].tlbe
;
2911 if (tlb
->prot
& PAGE_EXEC
)
2913 if (tlb
->prot
& PAGE_WRITE
)
2918 void helper_4xx_tlbwe_hi (target_ulong entry
, target_ulong val
)
2921 target_ulong page
, end
;
2923 #if defined (DEBUG_SOFTWARE_TLB)
2924 if (loglevel
!= 0) {
2925 fprintf(logfile
, "%s entry %d val " ADDRX
"\n", __func__
, (int)entry
, val
);
2929 tlb
= &env
->tlb
[entry
].tlbe
;
2930 /* Invalidate previous TLB (if it's valid) */
2931 if (tlb
->prot
& PAGE_VALID
) {
2932 end
= tlb
->EPN
+ tlb
->size
;
2933 #if defined (DEBUG_SOFTWARE_TLB)
2934 if (loglevel
!= 0) {
2935 fprintf(logfile
, "%s: invalidate old TLB %d start " ADDRX
2936 " end " ADDRX
"\n", __func__
, (int)entry
, tlb
->EPN
, end
);
2939 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
2940 tlb_flush_page(env
, page
);
2942 tlb
->size
= booke_tlb_to_page_size((val
>> 7) & 0x7);
2943 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2944 * If this ever occurs, one should use the ppcemb target instead
2945 * of the ppc or ppc64 one
2947 if ((val
& 0x40) && tlb
->size
< TARGET_PAGE_SIZE
) {
2948 cpu_abort(env
, "TLB size " TARGET_FMT_lu
" < %u "
2949 "are not supported (%d)\n",
2950 tlb
->size
, TARGET_PAGE_SIZE
, (int)((val
>> 7) & 0x7));
2952 tlb
->EPN
= val
& ~(tlb
->size
- 1);
2954 tlb
->prot
|= PAGE_VALID
;
2956 tlb
->prot
&= ~PAGE_VALID
;
2958 /* XXX: TO BE FIXED */
2959 cpu_abort(env
, "Little-endian TLB entries are not supported by now\n");
2961 tlb
->PID
= env
->spr
[SPR_40x_PID
]; /* PID */
2962 tlb
->attr
= val
& 0xFF;
2963 #if defined (DEBUG_SOFTWARE_TLB)
2964 if (loglevel
!= 0) {
2965 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
2966 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
2967 (int)entry
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
2968 tlb
->prot
& PAGE_READ
? 'r' : '-',
2969 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
2970 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
2971 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
2974 /* Invalidate new TLB (if valid) */
2975 if (tlb
->prot
& PAGE_VALID
) {
2976 end
= tlb
->EPN
+ tlb
->size
;
2977 #if defined (DEBUG_SOFTWARE_TLB)
2978 if (loglevel
!= 0) {
2979 fprintf(logfile
, "%s: invalidate TLB %d start " ADDRX
2980 " end " ADDRX
"\n", __func__
, (int)entry
, tlb
->EPN
, end
);
2983 for (page
= tlb
->EPN
; page
< end
; page
+= TARGET_PAGE_SIZE
)
2984 tlb_flush_page(env
, page
);
2988 void helper_4xx_tlbwe_lo (target_ulong entry
, target_ulong val
)
2992 #if defined (DEBUG_SOFTWARE_TLB)
2993 if (loglevel
!= 0) {
2994 fprintf(logfile
, "%s entry %i val " ADDRX
"\n", __func__
, (int)entry
, val
);
2998 tlb
= &env
->tlb
[entry
].tlbe
;
2999 tlb
->RPN
= val
& 0xFFFFFC00;
3000 tlb
->prot
= PAGE_READ
;
3002 tlb
->prot
|= PAGE_EXEC
;
3004 tlb
->prot
|= PAGE_WRITE
;
3005 #if defined (DEBUG_SOFTWARE_TLB)
3006 if (loglevel
!= 0) {
3007 fprintf(logfile
, "%s: set up TLB %d RPN " PADDRX
" EPN " ADDRX
3008 " size " ADDRX
" prot %c%c%c%c PID %d\n", __func__
,
3009 (int)entry
, tlb
->RPN
, tlb
->EPN
, tlb
->size
,
3010 tlb
->prot
& PAGE_READ
? 'r' : '-',
3011 tlb
->prot
& PAGE_WRITE
? 'w' : '-',
3012 tlb
->prot
& PAGE_EXEC
? 'x' : '-',
3013 tlb
->prot
& PAGE_VALID
? 'v' : '-', (int)tlb
->PID
);
3018 target_ulong
helper_4xx_tlbsx (target_ulong address
)
3020 return ppcemb_tlb_search(env
, address
, env
->spr
[SPR_40x_PID
]);
3023 /* PowerPC 440 TLB management */
3024 void helper_440_tlbwe (uint32_t word
, target_ulong entry
, target_ulong value
)
3027 target_ulong EPN
, RPN
, size
;
3030 #if defined (DEBUG_SOFTWARE_TLB)
3031 if (loglevel
!= 0) {
3032 fprintf(logfile
, "%s word %d entry %d value " ADDRX
"\n",
3033 __func__
, word
, (int)entry
, value
);
3038 tlb
= &env
->tlb
[entry
].tlbe
;
3041 /* Just here to please gcc */
3043 EPN
= value
& 0xFFFFFC00;
3044 if ((tlb
->prot
& PAGE_VALID
) && EPN
!= tlb
->EPN
)
3047 size
= booke_tlb_to_page_size((value
>> 4) & 0xF);
3048 if ((tlb
->prot
& PAGE_VALID
) && tlb
->size
< size
)
3052 tlb
->attr
|= (value
>> 8) & 1;
3053 if (value
& 0x200) {
3054 tlb
->prot
|= PAGE_VALID
;
3056 if (tlb
->prot
& PAGE_VALID
) {
3057 tlb
->prot
&= ~PAGE_VALID
;
3061 tlb
->PID
= env
->spr
[SPR_440_MMUCR
] & 0x000000FF;
3066 RPN
= value
& 0xFFFFFC0F;
3067 if ((tlb
->prot
& PAGE_VALID
) && tlb
->RPN
!= RPN
)
3072 tlb
->attr
= (tlb
->attr
& 0x1) | (value
& 0x0000FF00);
3073 tlb
->prot
= tlb
->prot
& PAGE_VALID
;
3075 tlb
->prot
|= PAGE_READ
<< 4;
3077 tlb
->prot
|= PAGE_WRITE
<< 4;
3079 tlb
->prot
|= PAGE_EXEC
<< 4;
3081 tlb
->prot
|= PAGE_READ
;
3083 tlb
->prot
|= PAGE_WRITE
;
3085 tlb
->prot
|= PAGE_EXEC
;
3090 target_ulong
helper_440_tlbre (uint32_t word
, target_ulong entry
)
3097 tlb
= &env
->tlb
[entry
].tlbe
;
3100 /* Just here to please gcc */
3103 size
= booke_page_size_to_tlb(tlb
->size
);
3104 if (size
< 0 || size
> 0xF)
3107 if (tlb
->attr
& 0x1)
3109 if (tlb
->prot
& PAGE_VALID
)
3111 env
->spr
[SPR_440_MMUCR
] &= ~0x000000FF;
3112 env
->spr
[SPR_440_MMUCR
] |= tlb
->PID
;
3118 ret
= tlb
->attr
& ~0x1;
3119 if (tlb
->prot
& (PAGE_READ
<< 4))
3121 if (tlb
->prot
& (PAGE_WRITE
<< 4))
3123 if (tlb
->prot
& (PAGE_EXEC
<< 4))
3125 if (tlb
->prot
& PAGE_READ
)
3127 if (tlb
->prot
& PAGE_WRITE
)
3129 if (tlb
->prot
& PAGE_EXEC
)
3136 target_ulong
helper_440_tlbsx (target_ulong address
)
3138 return ppcemb_tlb_search(env
, address
, env
->spr
[SPR_440_MMUCR
] & 0xFF);
3141 #endif /* !CONFIG_USER_ONLY */