hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "console.h"
  27 #include "net.h"
  28 #include "virtio-net.h"
  29
  30 //#define DEBUG_PCI
  31
  32 struct PCIBus {
  33     int bus_num;
  34     int devfn_min;
  35     pci_set_irq_fn set_irq;
  36     pci_map_irq_fn map_irq;
  37     uint32_t config_reg; /* XXX: suppress */
  38     /* low level pic */
  39     SetIRQFunc *low_set_irq;
  40     qemu_irq *irq_opaque;
  41     PCIDevice *devices[256];
  42     PCIDevice *parent_dev;
  43     PCIBus *next;
  44     /* The bus IRQ state is the logical OR of the connected devices.
  45        Keep a count of the number of devices with raised IRQs.  */
  46     int nirq;
  47     int irq_count[];
  48 };
  49
  50 static void pci_update_mappings(PCIDevice *d);
  51 static void pci_set_irq(void *opaque, int irq_num, int level);
  52
  53 target_phys_addr_t pci_mem_base;
  54 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  55 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  56 static int pci_irq_index;
  57 static PCIBus *first_bus;
  58
  59 static void pcibus_save(QEMUFile *f, void *opaque)
  60 {
  61     PCIBus *bus = (PCIBus *)opaque;
  62     int i;
  63
  64     qemu_put_be32(f, bus->nirq);
  65     for (i = 0; i < bus->nirq; i++)
  66         qemu_put_be32(f, bus->irq_count[i]);
  67 }
  68
  69 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  70 {
  71     PCIBus *bus = (PCIBus *)opaque;
  72     int i, nirq;
  73
  74     if (version_id != 1)
  75         return -EINVAL;
  76
  77     nirq = qemu_get_be32(f);
  78     if (bus->nirq != nirq) {
  79         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  80                 nirq, bus->nirq);
  81         return -EINVAL;
  82     }
  83
  84     for (i = 0; i < nirq; i++)
  85         bus->irq_count[i] = qemu_get_be32(f);
  86
  87     return 0;
  88 }
  89
  90 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  91                          qemu_irq *pic, int devfn_min, int nirq)
  92 {
  93     PCIBus *bus;
  94     static int nbus = 0;
  95
  96     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
  97     bus->set_irq = set_irq;
  98     bus->map_irq = map_irq;
  99     bus->irq_opaque = pic;
 100     bus->devfn_min = devfn_min;
 101     bus->nirq = nirq;
 102     first_bus = bus;
 103     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 104     return bus;
 105 }
 106
 107 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 108 {
 109     PCIBus *bus;
 110     bus = qemu_mallocz(sizeof(PCIBus));
 111     bus->map_irq = map_irq;
 112     bus->parent_dev = dev;
 113     bus->next = dev->bus->next;
 114     dev->bus->next = bus;
 115     return bus;
 116 }
 117
 118 int pci_bus_num(PCIBus *s)
 119 {
 120     return s->bus_num;
 121 }
 122
 123 void pci_device_save(PCIDevice *s, QEMUFile *f)
 124 {
 125     int i;
 126
 127     qemu_put_be32(f, 2); /* PCI device version */
 128     qemu_put_buffer(f, s->config, 256);
 129     for (i = 0; i < 4; i++)
 130         qemu_put_be32(f, s->irq_state[i]);
 131 }
 132
 133 int pci_device_load(PCIDevice *s, QEMUFile *f)
 134 {
 135     uint32_t version_id;
 136     int i;
 137
 138     version_id = qemu_get_be32(f);
 139     if (version_id > 2)
 140         return -EINVAL;
 141     qemu_get_buffer(f, s->config, 256);
 142     pci_update_mappings(s);
 143
 144     if (version_id >= 2)
 145         for (i = 0; i < 4; i ++)
 146             s->irq_state[i] = qemu_get_be32(f);
 147
 148     return 0;
 149 }
 150
 151 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 152 {
 153     uint16_t *id;
 154
 155     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 156     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 157     id[1] = cpu_to_le16(pci_default_sub_device_id);
 158     return 0;
 159 }
 160
 161 /* -1 for devfn means auto assign */
 162 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 163                                int instance_size, int devfn,
 164                                PCIConfigReadFunc *config_read,
 165                                PCIConfigWriteFunc *config_write)
 166 {
 167     PCIDevice *pci_dev;
 168
 169     if (pci_irq_index >= PCI_DEVICES_MAX)
 170         return NULL;
 171
 172     if (devfn < 0) {
 173         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 174             if (!bus->devices[devfn])
 175                 goto found;
 176         }
 177         return NULL;
 178     found: ;
 179     }
 180     pci_dev = qemu_mallocz(instance_size);
 181     pci_dev->bus = bus;
 182     pci_dev->devfn = devfn;
 183     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 184     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 185     pci_set_default_subsystem_id(pci_dev);
 186
 187     if (!config_read)
 188         config_read = pci_default_read_config;
 189     if (!config_write)
 190         config_write = pci_default_write_config;
 191     pci_dev->config_read = config_read;
 192     pci_dev->config_write = config_write;
 193     pci_dev->irq_index = pci_irq_index++;
 194     bus->devices[devfn] = pci_dev;
 195     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 196     return pci_dev;
 197 }
 198
 199 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 200 {
 201     return addr + pci_mem_base;
 202 }
 203
 204 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 205 {
 206     PCIIORegion *r;
 207     int i;
 208
 209     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 210         r = &pci_dev->io_regions[i];
 211         if (!r->size || r->addr == -1)
 212             continue;
 213         if (r->type == PCI_ADDRESS_SPACE_IO) {
 214             isa_unassign_ioport(r->addr, r->size);
 215         } else {
 216             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 217                                                      r->size,
 218                                                      IO_MEM_UNASSIGNED);
 219         }
 220     }
 221 }
 222
 223 int pci_unregister_device(PCIDevice *pci_dev)
 224 {
 225     int ret = 0;
 226
 227     if (pci_dev->unregister)
 228         ret = pci_dev->unregister(pci_dev);
 229     if (ret)
 230         return ret;
 231
 232     pci_unregister_io_regions(pci_dev);
 233
 234     qemu_free_irqs(pci_dev->irq);
 235     pci_irq_index--;
 236     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 237     qemu_free(pci_dev);
 238     return 0;
 239 }
 240
 241 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 242                             uint32_t size, int type,
 243                             PCIMapIORegionFunc *map_func)
 244 {
 245     PCIIORegion *r;
 246     uint32_t addr;
 247
 248     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 249         return;
 250     r = &pci_dev->io_regions[region_num];
 251     r->addr = -1;
 252     r->size = size;
 253     r->type = type;
 254     r->map_func = map_func;
 255     if (region_num == PCI_ROM_SLOT) {
 256         addr = 0x30;
 257     } else {
 258         addr = 0x10 + region_num * 4;
 259     }
 260     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 261 }
 262
 263 static void pci_update_mappings(PCIDevice *d)
 264 {
 265     PCIIORegion *r;
 266     int cmd, i;
 267     uint32_t last_addr, new_addr, config_ofs;
 268
 269     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 270     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 271         r = &d->io_regions[i];
 272         if (i == PCI_ROM_SLOT) {
 273             config_ofs = 0x30;
 274         } else {
 275             config_ofs = 0x10 + i * 4;
 276         }
 277         if (r->size != 0) {
 278             if (r->type & PCI_ADDRESS_SPACE_IO) {
 279                 if (cmd & PCI_COMMAND_IO) {
 280                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 281                                                          config_ofs));
 282                     new_addr = new_addr & ~(r->size - 1);
 283                     last_addr = new_addr + r->size - 1;
 284                     /* NOTE: we have only 64K ioports on PC */
 285                     if (last_addr <= new_addr || new_addr == 0 ||
 286                         last_addr >= 0x10000) {
 287                         new_addr = -1;
 288                     }
 289                 } else {
 290                     new_addr = -1;
 291                 }
 292             } else {
 293                 if (cmd & PCI_COMMAND_MEMORY) {
 294                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 295                                                          config_ofs));
 296                     /* the ROM slot has a specific enable bit */
 297                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 298                         goto no_mem_map;
 299                     new_addr = new_addr & ~(r->size - 1);
 300                     last_addr = new_addr + r->size - 1;
 301                     /* NOTE: we do not support wrapping */
 302                     /* XXX: as we cannot support really dynamic
 303                        mappings, we handle specific values as invalid
 304                        mappings. */
 305                     if (last_addr <= new_addr || new_addr == 0 ||
 306                         last_addr == -1) {
 307                         new_addr = -1;
 308                     }
 309                 } else {
 310                 no_mem_map:
 311                     new_addr = -1;
 312                 }
 313             }
 314             /* now do the real mapping */
 315             if (new_addr != r->addr) {
 316                 if (r->addr != -1) {
 317                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 318                         int class;
 319                         /* NOTE: specific hack for IDE in PC case:
 320                            only one byte must be mapped. */
 321                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 322                         if (class == 0x0101 && r->size == 4) {
 323                             isa_unassign_ioport(r->addr + 2, 1);
 324                         } else {
 325                             isa_unassign_ioport(r->addr, r->size);
 326                         }
 327                     } else {
 328                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 329                                                      r->size,
 330                                                      IO_MEM_UNASSIGNED);
 331                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 332                     }
 333                 }
 334                 r->addr = new_addr;
 335                 if (r->addr != -1) {
 336                     r->map_func(d, i, r->addr, r->size, r->type);
 337                 }
 338             }
 339         }
 340     }
 341 }
 342
 343 uint32_t pci_default_read_config(PCIDevice *d,
 344                                  uint32_t address, int len)
 345 {
 346     uint32_t val;
 347
 348     switch(len) {
 349     default:
 350     case 4:
 351         if (address <= 0xfc) {
 352             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 353             break;
 354         }
 355         /* fall through */
 356     case 2:
 357         if (address <= 0xfe) {
 358             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 359             break;
 360         }
 361         /* fall through */
 362     case 1:
 363         val = d->config[address];
 364         break;
 365     }
 366     return val;
 367 }
 368
 369 void pci_default_write_config(PCIDevice *d,
 370                               uint32_t address, uint32_t val, int len)
 371 {
 372     int can_write, i;
 373     uint32_t end, addr;
 374
 375     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 376                      (address >= 0x30 && address < 0x34))) {
 377         PCIIORegion *r;
 378         int reg;
 379
 380         if ( address >= 0x30 ) {
 381             reg = PCI_ROM_SLOT;
 382         }else{
 383             reg = (address - 0x10) >> 2;
 384         }
 385         r = &d->io_regions[reg];
 386         if (r->size == 0)
 387             goto default_config;
 388         /* compute the stored value */
 389         if (reg == PCI_ROM_SLOT) {
 390             /* keep ROM enable bit */
 391             val &= (~(r->size - 1)) | 1;
 392         } else {
 393             val &= ~(r->size - 1);
 394             val |= r->type;
 395         }
 396         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 397         pci_update_mappings(d);
 398         return;
 399     }
 400  default_config:
 401     /* not efficient, but simple */
 402     addr = address;
 403     for(i = 0; i < len; i++) {
 404         /* default read/write accesses */
 405         switch(d->config[0x0e]) {
 406         case 0x00:
 407         case 0x80:
 408             switch(addr) {
 409             case 0x00:
 410             case 0x01:
 411             case 0x02:
 412             case 0x03:
 413             case 0x08:
 414             case 0x09:
 415             case 0x0a:
 416             case 0x0b:
 417             case 0x0e:
 418             case 0x10 ... 0x27: /* base */
 419             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 420             case 0x30 ... 0x33: /* rom */
 421             case 0x3d:
 422                 can_write = 0;
 423                 break;
 424             default:
 425                 can_write = 1;
 426                 break;
 427             }
 428             break;
 429         default:
 430         case 0x01:
 431             switch(addr) {
 432             case 0x00:
 433             case 0x01:
 434             case 0x02:
 435             case 0x03:
 436             case 0x08:
 437             case 0x09:
 438             case 0x0a:
 439             case 0x0b:
 440             case 0x0e:
 441             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 442             case 0x38 ... 0x3b: /* rom */
 443             case 0x3d:
 444                 can_write = 0;
 445                 break;
 446             default:
 447                 can_write = 1;
 448                 break;
 449             }
 450             break;
 451         }
 452         if (can_write) {
 453             /* Mask out writes to reserved bits in registers */
 454             switch (addr) {
 455             case 0x05:
 456                 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
 457                 break;
 458             case 0x06:
 459                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
 460                 break;
 461             case 0x07:
 462                 val &= ~PCI_STATUS_RESERVED_MASK_HI;
 463                 break;
 464             }
 465             d->config[addr] = val;
 466         }
 467         if (++addr > 0xff)
 468                 break;
 469         val >>= 8;
 470     }
 471
 472     end = address + len;
 473     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 474         /* if the command register is modified, we must modify the mappings */
 475         pci_update_mappings(d);
 476     }
 477 }
 478
 479 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 480 {
 481     PCIBus *s = opaque;
 482     PCIDevice *pci_dev;
 483     int config_addr, bus_num;
 484
 485 #if defined(DEBUG_PCI) && 0
 486     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 487            addr, val, len);
 488 #endif
 489     bus_num = (addr >> 16) & 0xff;
 490     while (s && s->bus_num != bus_num)
 491         s = s->next;
 492     if (!s)
 493         return;
 494     pci_dev = s->devices[(addr >> 8) & 0xff];
 495     if (!pci_dev)
 496         return;
 497     config_addr = addr & 0xff;
 498 #if defined(DEBUG_PCI)
 499     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 500            pci_dev->name, config_addr, val, len);
 501 #endif
 502     pci_dev->config_write(pci_dev, config_addr, val, len);
 503 }
 504
 505 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 506 {
 507     PCIBus *s = opaque;
 508     PCIDevice *pci_dev;
 509     int config_addr, bus_num;
 510     uint32_t val;
 511
 512     bus_num = (addr >> 16) & 0xff;
 513     while (s && s->bus_num != bus_num)
 514         s= s->next;
 515     if (!s)
 516         goto fail;
 517     pci_dev = s->devices[(addr >> 8) & 0xff];
 518     if (!pci_dev) {
 519     fail:
 520         switch(len) {
 521         case 1:
 522             val = 0xff;
 523             break;
 524         case 2:
 525             val = 0xffff;
 526             break;
 527         default:
 528         case 4:
 529             val = 0xffffffff;
 530             break;
 531         }
 532         goto the_end;
 533     }
 534     config_addr = addr & 0xff;
 535     val = pci_dev->config_read(pci_dev, config_addr, len);
 536 #if defined(DEBUG_PCI)
 537     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 538            pci_dev->name, config_addr, val, len);
 539 #endif
 540  the_end:
 541 #if defined(DEBUG_PCI) && 0
 542     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 543            addr, val, len);
 544 #endif
 545     return val;
 546 }
 547
 548 /***********************************************************/
 549 /* generic PCI irq support */
 550
 551 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 552 static void pci_set_irq(void *opaque, int irq_num, int level)
 553 {
 554     PCIDevice *pci_dev = (PCIDevice *)opaque;
 555     PCIBus *bus;
 556     int change;
 557
 558     change = level - pci_dev->irq_state[irq_num];
 559     if (!change)
 560         return;
 561
 562     pci_dev->irq_state[irq_num] = level;
 563     for (;;) {
 564         bus = pci_dev->bus;
 565         irq_num = bus->map_irq(pci_dev, irq_num);
 566         if (bus->set_irq)
 567             break;
 568         pci_dev = bus->parent_dev;
 569     }
 570     bus->irq_count[irq_num] += change;
 571     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 572 }
 573
 574 /***********************************************************/
 575 /* monitor info on PCI */
 576
 577 typedef struct {
 578     uint16_t class;
 579     const char *desc;
 580 } pci_class_desc;
 581
 582 static const pci_class_desc pci_class_descriptions[] =
 583 {
 584     { 0x0100, "SCSI controller"},
 585     { 0x0101, "IDE controller"},
 586     { 0x0102, "Floppy controller"},
 587     { 0x0103, "IPI controller"},
 588     { 0x0104, "RAID controller"},
 589     { 0x0106, "SATA controller"},
 590     { 0x0107, "SAS controller"},
 591     { 0x0180, "Storage controller"},
 592     { 0x0200, "Ethernet controller"},
 593     { 0x0201, "Token Ring controller"},
 594     { 0x0202, "FDDI controller"},
 595     { 0x0203, "ATM controller"},
 596     { 0x0280, "Network controller"},
 597     { 0x0300, "VGA controller"},
 598     { 0x0301, "XGA controller"},
 599     { 0x0302, "3D controller"},
 600     { 0x0380, "Display controller"},
 601     { 0x0400, "Video controller"},
 602     { 0x0401, "Audio controller"},
 603     { 0x0402, "Phone"},
 604     { 0x0480, "Multimedia controller"},
 605     { 0x0500, "RAM controller"},
 606     { 0x0501, "Flash controller"},
 607     { 0x0580, "Memory controller"},
 608     { 0x0600, "Host bridge"},
 609     { 0x0601, "ISA bridge"},
 610     { 0x0602, "EISA bridge"},
 611     { 0x0603, "MC bridge"},
 612     { 0x0604, "PCI bridge"},
 613     { 0x0605, "PCMCIA bridge"},
 614     { 0x0606, "NUBUS bridge"},
 615     { 0x0607, "CARDBUS bridge"},
 616     { 0x0608, "RACEWAY bridge"},
 617     { 0x0680, "Bridge"},
 618     { 0x0c03, "USB controller"},
 619     { 0, NULL}
 620 };
 621
 622 static void pci_info_device(PCIDevice *d)
 623 {
 624     int i, class;
 625     PCIIORegion *r;
 626     const pci_class_desc *desc;
 627
 628     term_printf("  Bus %2d, device %3d, function %d:\n",
 629            d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 630     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 631     term_printf("    ");
 632     desc = pci_class_descriptions;
 633     while (desc->desc && class != desc->class)
 634         desc++;
 635     if (desc->desc) {
 636         term_printf("%s", desc->desc);
 637     } else {
 638         term_printf("Class %04x", class);
 639     }
 640     term_printf(": PCI device %04x:%04x\n",
 641            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 642            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 643
 644     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 645         term_printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
 646     }
 647     if (class == 0x0604) {
 648         term_printf("      BUS %d.\n", d->config[0x19]);
 649     }
 650     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 651         r = &d->io_regions[i];
 652         if (r->size != 0) {
 653             term_printf("      BAR%d: ", i);
 654             if (r->type & PCI_ADDRESS_SPACE_IO) {
 655                 term_printf("I/O at 0x%04x [0x%04x].\n",
 656                        r->addr, r->addr + r->size - 1);
 657             } else {
 658                 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
 659                        r->addr, r->addr + r->size - 1);
 660             }
 661         }
 662     }
 663     if (class == 0x0604 && d->config[0x19] != 0) {
 664         pci_for_each_device(d->config[0x19], pci_info_device);
 665     }
 666 }
 667
 668 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 669 {
 670     PCIBus *bus = first_bus;
 671     PCIDevice *d;
 672     int devfn;
 673
 674     while (bus && bus->bus_num != bus_num)
 675         bus = bus->next;
 676     if (bus) {
 677         for(devfn = 0; devfn < 256; devfn++) {
 678             d = bus->devices[devfn];
 679             if (d)
 680                 fn(d);
 681         }
 682     }
 683 }
 684
 685 void pci_info(void)
 686 {
 687     pci_for_each_device(0, pci_info_device);
 688 }
 689
 690 static const char * const pci_nic_models[] = {
 691     "ne2k_pci",
 692     "i82551",
 693     "i82557b",
 694     "i82559er",
 695     "rtl8139",
 696     "e1000",
 697     "pcnet",
 698     "virtio",
 699     NULL
 700 };
 701
 702 typedef PCIDevice *(*PCINICInitFn)(PCIBus *, NICInfo *, int);
 703
 704 static PCINICInitFn pci_nic_init_fns[] = {
 705     pci_ne2000_init,
 706     pci_i82551_init,
 707     pci_i82557b_init,
 708     pci_i82559er_init,
 709     pci_rtl8139_init,
 710     pci_e1000_init,
 711     pci_pcnet_init,
 712     virtio_net_init,
 713     NULL
 714 };
 715
 716 /* Initialize a PCI NIC.  */
 717 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 718                   const char *default_model)
 719 {
 720     PCIDevice *pci_dev;
 721     int i;
 722
 723     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 724
 725     for (i = 0; pci_nic_models[i]; i++)
 726         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 727             pci_dev = pci_nic_init_fns[i](bus, nd, devfn);
 728             if (pci_dev)
 729                 nd->private = pci_dev;
 730             return pci_dev;
 731         }
 732
 733     return NULL;
 734 }
 735
 736 typedef struct {
 737     PCIDevice dev;
 738     PCIBus *bus;
 739 } PCIBridge;
 740
 741 static void pci_bridge_write_config(PCIDevice *d,
 742                              uint32_t address, uint32_t val, int len)
 743 {
 744     PCIBridge *s = (PCIBridge *)d;
 745
 746     if (address == 0x19 || (address == 0x18 && len > 1)) {
 747         if (address == 0x19)
 748             s->bus->bus_num = val & 0xff;
 749         else
 750             s->bus->bus_num = (val >> 8) & 0xff;
 751 #if defined(DEBUG_PCI)
 752         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 753 #endif
 754     }
 755     pci_default_write_config(d, address, val, len);
 756 }
 757
 758 PCIBus *pci_find_bus(int bus_num)
 759 {
 760     PCIBus *bus = first_bus;
 761
 762     while (bus && bus->bus_num != bus_num)
 763         bus = bus->next;
 764
 765     return bus;
 766 }
 767
 768 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 769 {
 770     PCIBus *bus = pci_find_bus(bus_num);
 771
 772     if (!bus)
 773         return NULL;
 774
 775     return bus->devices[PCI_DEVFN(slot, function)];
 776 }
 777
 778 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 779                         pci_map_irq_fn map_irq, const char *name)
 780 {
 781     PCIBridge *s;
 782     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 783                                          devfn, NULL, pci_bridge_write_config);
 784
 785     pci_config_set_vendor_id(s->dev.config, vid);
 786     pci_config_set_device_id(s->dev.config, did);
 787
 788     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 789     s->dev.config[0x05] = 0x00;
 790     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 791     s->dev.config[0x07] = 0x00; // status = fast devsel
 792     s->dev.config[0x08] = 0x00; // revision
 793     s->dev.config[0x09] = 0x00; // programming i/f
 794     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 795     s->dev.config[0x0D] = 0x10; // latency_timer
 796     s->dev.config[0x0E] = 0x81; // header_type
 797     s->dev.config[0x1E] = 0xa0; // secondary status
 798
 799     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
 800     return s->bus;
 801 }