From e2ea21b39660eb6938cb26a36248e23361d9534d Mon Sep 17 00:00:00 2001 From: blueswir1 Date: Wed, 10 Sep 2008 19:57:35 +0000 Subject: [PATCH] Convert basic 64 bit VIS ops to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-sparc/TODO | 2 - target-sparc/helper.h | 9 ---- target-sparc/op_helper.c | 45 ------------------- target-sparc/translate.c | 111 +++++++++++++++++++++++++++-------------------- 4 files changed, 65 insertions(+), 102 deletions(-) diff --git a/target-sparc/TODO b/target-sparc/TODO index 70bdeeca71..62b0f47d18 100644 --- a/target-sparc/TODO +++ b/target-sparc/TODO @@ -39,8 +39,6 @@ Sparc64 CPUs: - Full hypervisor support - SMP/CMT - Sun4v CPUs -- Optimizations/improvements: - - Use TCG logic ops for VIS when possible Sun4: - To be added diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 1c16b25fcb..14ca509777 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -139,15 +139,6 @@ F_HELPER_0_0(dtox); F_HELPER_0_0(qtox); F_HELPER_0_0(aligndata); -F_HELPER_0_0(not); -F_HELPER_0_0(nor); -F_HELPER_0_0(or); -F_HELPER_0_0(xor); -F_HELPER_0_0(and); -F_HELPER_0_0(ornot); -F_HELPER_0_0(andnot); -F_HELPER_0_0(nand); -F_HELPER_0_0(xnor); F_HELPER_0_0(pmerge); F_HELPER_0_0(mul8x16); F_HELPER_0_0(mul8x16al); diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 895e7ec380..0f289b6ede 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -246,51 +246,6 @@ void helper_faligndata(void) *((uint64_t *)&DT0) = tmp; } -void helper_fnot(void) -{ - *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1; -} - -void helper_fnor(void) -{ - *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1); -} - -void helper_for(void) -{ - *(uint64_t *)&DT0 |= *(uint64_t *)&DT1; -} - -void helper_fxor(void) -{ - *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1; -} - -void helper_fand(void) -{ - *(uint64_t *)&DT0 &= *(uint64_t *)&DT1; -} - -void helper_fornot(void) -{ - *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1; -} - -void helper_fandnot(void) -{ - *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1; -} - -void helper_fnand(void) -{ - *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1); -} - -void helper_fxnor(void) -{ - *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1; -} - #ifdef WORDS_BIGENDIAN #define VIS_B64(n) b[7 - (n)] #define VIS_W64(n) w[3 - (n)] diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 017f4c6008..e36de56057 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3886,10 +3886,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x062: /* VIS I fnor */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fnor); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); + tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); break; case 0x063: /* VIS I fnors */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3898,10 +3900,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x064: /* VIS I fandnot2 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT1(DFPREG(rs1)); - gen_op_load_fpr_DT0(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fandnot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x065: /* VIS I fandnot2s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3910,9 +3914,10 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x066: /* VIS I fnot2 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fnot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], + -1); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs2) + 1], -1); break; case 0x067: /* VIS I fnot2s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3920,10 +3925,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fandnot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs1)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs1) + 1]); break; case 0x069: /* VIS I fandnot1s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3932,9 +3939,10 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x06a: /* VIS I fnot1 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT1(DFPREG(rs1)); - tcg_gen_helper_0_0(helper_fnot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + -1); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], -1); break; case 0x06b: /* VIS I fnot1s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3942,10 +3950,11 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fxor); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x06d: /* VIS I fxors */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3953,10 +3962,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x06e: /* VIS I fnand */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fnand); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); + tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); break; case 0x06f: /* VIS I fnands */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3965,10 +3976,11 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x070: /* VIS I fand */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fand); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x071: /* VIS I fands */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3976,10 +3988,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x072: /* VIS I fxnor */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fxnor); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs1)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs1) + 1]); break; case 0x073: /* VIS I fxnors */ CHECK_FPU_FEATURE(dc, VIS1); @@ -3998,10 +4012,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT1(DFPREG(rs1)); - gen_op_load_fpr_DT0(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fornot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs2)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x077: /* VIS I fornot2s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4019,10 +4035,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fornot); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, + cpu_fpr[DFPREG(rs1)]); + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, + cpu_fpr[DFPREG(rs1) + 1]); break; case 0x07b: /* VIS I fornot1s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4031,10 +4049,11 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x07c: /* VIS I for */ CHECK_FPU_FEATURE(dc, VIS1); - gen_op_load_fpr_DT0(DFPREG(rs1)); - gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_for); - gen_op_store_DT0_fpr(DFPREG(rd)); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], + cpu_fpr[DFPREG(rs2)]); + tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], + cpu_fpr[DFPREG(rs1) + 1], + cpu_fpr[DFPREG(rs2) + 1]); break; case 0x07d: /* VIS I fors */ CHECK_FPU_FEATURE(dc, VIS1); -- 2.11.4.GIT