2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * o Isochronous transfers
23 * o Allocate bandwidth in frames properly
24 * o Disable timers when nothing needs to be done, or remove timer usage
26 * o Handle unrecoverable errors properly
27 * o BIOS work to boot from USB storage
33 /* Dump packet contents. */
34 //#define DEBUG_PACKET
35 /* This causes frames to occur 1000x slower */
36 //#define OHCI_TIME_WARP 1
39 #define dprintf printf
44 /* Number of Downstream Ports on the root hub. */
46 #define OHCI_MAX_PORTS 15
48 static int64_t usb_frame_time
;
49 static int64_t usb_bit_time
;
51 typedef struct OHCIPort
{
65 target_phys_addr_t mem_base
;
74 /* Control partition */
79 /* memory pointer partition */
81 uint32_t ctrl_head
, ctrl_cur
;
82 uint32_t bulk_head
, bulk_cur
;
87 /* Frame counter partition */
92 uint16_t frame_number
;
97 /* Root Hub partition */
98 uint32_t rhdesc_a
, rhdesc_b
;
100 OHCIPort rhport
[OHCI_MAX_PORTS
];
102 /* PXA27x Non-OHCI events */
108 /* Active packets. */
110 USBPacket usb_packet
;
111 uint8_t usb_buf
[8192];
117 /* Host Controller Communications Area */
124 /* Bitfields for the first word of an Endpoint Desciptor. */
125 #define OHCI_ED_FA_SHIFT 0
126 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
127 #define OHCI_ED_EN_SHIFT 7
128 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
129 #define OHCI_ED_D_SHIFT 11
130 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
131 #define OHCI_ED_S (1<<13)
132 #define OHCI_ED_K (1<<14)
133 #define OHCI_ED_F (1<<15)
134 #define OHCI_ED_MPS_SHIFT 7
135 #define OHCI_ED_MPS_MASK (0xf<<OHCI_ED_FA_SHIFT)
137 /* Flags in the head field of an Endpoint Desciptor. */
141 /* Bitfields for the first word of a Transfer Desciptor. */
142 #define OHCI_TD_R (1<<18)
143 #define OHCI_TD_DP_SHIFT 19
144 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
145 #define OHCI_TD_DI_SHIFT 21
146 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
147 #define OHCI_TD_T0 (1<<24)
148 #define OHCI_TD_T1 (1<<24)
149 #define OHCI_TD_EC_SHIFT 26
150 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
151 #define OHCI_TD_CC_SHIFT 28
152 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
154 #define OHCI_DPTR_MASK 0xfffffff0
156 #define OHCI_BM(val, field) \
157 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
159 #define OHCI_SET_BM(val, field, newval) do { \
160 val &= ~OHCI_##field##_MASK; \
161 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
164 /* endpoint descriptor */
172 /* General transfer descriptor */
180 #define USB_HZ 12000000
182 /* OHCI Local stuff */
183 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
184 #define OHCI_CTL_PLE (1<<2)
185 #define OHCI_CTL_IE (1<<3)
186 #define OHCI_CTL_CLE (1<<4)
187 #define OHCI_CTL_BLE (1<<5)
188 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
189 #define OHCI_USB_RESET 0x00
190 #define OHCI_USB_RESUME 0x40
191 #define OHCI_USB_OPERATIONAL 0x80
192 #define OHCI_USB_SUSPEND 0xc0
193 #define OHCI_CTL_IR (1<<8)
194 #define OHCI_CTL_RWC (1<<9)
195 #define OHCI_CTL_RWE (1<<10)
197 #define OHCI_STATUS_HCR (1<<0)
198 #define OHCI_STATUS_CLF (1<<1)
199 #define OHCI_STATUS_BLF (1<<2)
200 #define OHCI_STATUS_OCR (1<<3)
201 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
203 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
204 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
205 #define OHCI_INTR_SF (1<<2) /* Start of frame */
206 #define OHCI_INTR_RD (1<<3) /* Resume detect */
207 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
208 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
209 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
210 #define OHCI_INTR_OC (1<<30) /* Ownership change */
211 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
213 #define OHCI_HCCA_SIZE 0x100
214 #define OHCI_HCCA_MASK 0xffffff00
216 #define OHCI_EDPTR_MASK 0xfffffff0
218 #define OHCI_FMI_FI 0x00003fff
219 #define OHCI_FMI_FSMPS 0xffff0000
220 #define OHCI_FMI_FIT 0x80000000
222 #define OHCI_FR_RT (1<<31)
224 #define OHCI_LS_THRESH 0x628
226 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
227 #define OHCI_RHA_PSM (1<<8)
228 #define OHCI_RHA_NPS (1<<9)
229 #define OHCI_RHA_DT (1<<10)
230 #define OHCI_RHA_OCPM (1<<11)
231 #define OHCI_RHA_NOCP (1<<12)
232 #define OHCI_RHA_POTPGT_MASK 0xff000000
234 #define OHCI_RHS_LPS (1<<0)
235 #define OHCI_RHS_OCI (1<<1)
236 #define OHCI_RHS_DRWE (1<<15)
237 #define OHCI_RHS_LPSC (1<<16)
238 #define OHCI_RHS_OCIC (1<<17)
239 #define OHCI_RHS_CRWE (1<<31)
241 #define OHCI_PORT_CCS (1<<0)
242 #define OHCI_PORT_PES (1<<1)
243 #define OHCI_PORT_PSS (1<<2)
244 #define OHCI_PORT_POCI (1<<3)
245 #define OHCI_PORT_PRS (1<<4)
246 #define OHCI_PORT_PPS (1<<8)
247 #define OHCI_PORT_LSDA (1<<9)
248 #define OHCI_PORT_CSC (1<<16)
249 #define OHCI_PORT_PESC (1<<17)
250 #define OHCI_PORT_PSSC (1<<18)
251 #define OHCI_PORT_OCIC (1<<19)
252 #define OHCI_PORT_PRSC (1<<20)
253 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
254 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
256 #define OHCI_TD_DIR_SETUP 0x0
257 #define OHCI_TD_DIR_OUT 0x1
258 #define OHCI_TD_DIR_IN 0x2
259 #define OHCI_TD_DIR_RESERVED 0x3
261 #define OHCI_CC_NOERROR 0x0
262 #define OHCI_CC_CRC 0x1
263 #define OHCI_CC_BITSTUFFING 0x2
264 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
265 #define OHCI_CC_STALL 0x4
266 #define OHCI_CC_DEVICENOTRESPONDING 0x5
267 #define OHCI_CC_PIDCHECKFAILURE 0x6
268 #define OHCI_CC_UNDEXPETEDPID 0x7
269 #define OHCI_CC_DATAOVERRUN 0x8
270 #define OHCI_CC_DATAUNDERRUN 0x9
271 #define OHCI_CC_BUFFEROVERRUN 0xc
272 #define OHCI_CC_BUFFERUNDERRUN 0xd
274 #define OHCI_HRESET_FSBIR (1 << 0)
276 /* Update IRQ levels */
277 static inline void ohci_intr_update(OHCIState
*ohci
)
281 if ((ohci
->intr
& OHCI_INTR_MIE
) &&
282 (ohci
->intr_status
& ohci
->intr
))
285 if (ohci
->type
== OHCI_TYPE_PCI
)
286 pci_set_irq((PCIDevice
*)ohci
->pic
, ohci
->irq
, level
);
288 pic_set_irq_new(ohci
->pic
, ohci
->irq
, level
);
291 /* Set an interrupt */
292 static inline void ohci_set_interrupt(OHCIState
*ohci
, uint32_t intr
)
294 ohci
->intr_status
|= intr
;
295 ohci_intr_update(ohci
);
298 /* Attach or detach a device on a root hub port. */
299 static void ohci_attach(USBPort
*port1
, USBDevice
*dev
)
301 OHCIState
*s
= port1
->opaque
;
302 OHCIPort
*port
= &s
->rhport
[port1
->index
];
303 uint32_t old_state
= port
->ctrl
;
306 if (port
->port
.dev
) {
307 usb_attach(port1
, NULL
);
309 /* set connect status */
310 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
313 if (dev
->speed
== USB_SPEED_LOW
)
314 port
->ctrl
|= OHCI_PORT_LSDA
;
316 port
->ctrl
&= ~OHCI_PORT_LSDA
;
317 port
->port
.dev
= dev
;
319 /* notify of remote-wakeup */
320 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
)
321 ohci_set_interrupt(s
, OHCI_INTR_RD
);
323 /* send the attach message */
324 usb_send_msg(dev
, USB_MSG_ATTACH
);
325 dprintf("usb-ohci: Attached port %d\n", port1
->index
);
327 /* set connect status */
328 if (port
->ctrl
& OHCI_PORT_CCS
) {
329 port
->ctrl
&= ~OHCI_PORT_CCS
;
330 port
->ctrl
|= OHCI_PORT_CSC
;
333 if (port
->ctrl
& OHCI_PORT_PES
) {
334 port
->ctrl
&= ~OHCI_PORT_PES
;
335 port
->ctrl
|= OHCI_PORT_PESC
;
337 dev
= port
->port
.dev
;
339 /* send the detach message */
340 usb_send_msg(dev
, USB_MSG_DETACH
);
342 port
->port
.dev
= NULL
;
343 dprintf("usb-ohci: Detached port %d\n", port1
->index
);
346 if (old_state
!= port
->ctrl
)
347 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
350 /* Reset the controller */
351 static void ohci_reset(OHCIState
*ohci
)
359 ohci
->intr_status
= 0;
360 ohci
->intr
= OHCI_INTR_MIE
;
363 ohci
->ctrl_head
= ohci
->ctrl_cur
= 0;
364 ohci
->bulk_head
= ohci
->bulk_cur
= 0;
367 ohci
->done_count
= 7;
369 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
370 * I took the value linux sets ...
372 ohci
->fsmps
= 0x2778;
376 ohci
->frame_number
= 0;
378 ohci
->lst
= OHCI_LS_THRESH
;
380 ohci
->rhdesc_a
= OHCI_RHA_NPS
| ohci
->num_ports
;
381 ohci
->rhdesc_b
= 0x0; /* Impl. specific */
384 for (i
= 0; i
< ohci
->num_ports
; i
++)
386 port
= &ohci
->rhport
[i
];
389 ohci_attach(&port
->port
, port
->port
.dev
);
391 if (ohci
->async_td
) {
392 usb_cancel_packet(&ohci
->usb_packet
);
395 dprintf("usb-ohci: Reset %s\n", ohci
->name
);
398 /* Get an array of dwords from main memory */
399 static inline int get_dwords(uint32_t addr
, uint32_t *buf
, int num
)
403 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
404 cpu_physical_memory_rw(addr
, (uint8_t *)buf
, sizeof(*buf
), 0);
405 *buf
= le32_to_cpu(*buf
);
411 /* Put an array of dwords in to main memory */
412 static inline int put_dwords(uint32_t addr
, uint32_t *buf
, int num
)
416 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
417 uint32_t tmp
= cpu_to_le32(*buf
);
418 cpu_physical_memory_rw(addr
, (uint8_t *)&tmp
, sizeof(tmp
), 1);
424 static inline int ohci_read_ed(uint32_t addr
, struct ohci_ed
*ed
)
426 return get_dwords(addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
429 static inline int ohci_read_td(uint32_t addr
, struct ohci_td
*td
)
431 return get_dwords(addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
434 static inline int ohci_put_ed(uint32_t addr
, struct ohci_ed
*ed
)
436 return put_dwords(addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
439 static inline int ohci_put_td(uint32_t addr
, struct ohci_td
*td
)
441 return put_dwords(addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
444 /* Read/Write the contents of a TD from/to main memory. */
445 static void ohci_copy_td(struct ohci_td
*td
, uint8_t *buf
, int len
, int write
)
451 n
= 0x1000 - (ptr
& 0xfff);
454 cpu_physical_memory_rw(ptr
, buf
, n
, write
);
457 ptr
= td
->be
& ~0xfffu
;
459 cpu_physical_memory_rw(ptr
, buf
, len
- n
, write
);
462 static void ohci_process_lists(OHCIState
*ohci
);
464 static void ohci_async_complete_packet(USBPacket
* packet
, void *opaque
)
466 OHCIState
*ohci
= opaque
;
468 dprintf("Async packet complete\n");
470 ohci
->async_complete
= 1;
471 ohci_process_lists(ohci
);
474 /* Service a transport descriptor.
475 Returns nonzero to terminate processing of this endpoint. */
477 static int ohci_service_td(OHCIState
*ohci
, struct ohci_ed
*ed
)
491 addr
= ed
->head
& OHCI_DPTR_MASK
;
492 /* See if this TD has already been submitted to the device. */
493 completion
= (addr
== ohci
->async_td
);
494 if (completion
&& !ohci
->async_complete
) {
496 dprintf("Skipping async TD\n");
500 if (!ohci_read_td(addr
, &td
)) {
501 fprintf(stderr
, "usb-ohci: TD read error at %x\n", addr
);
505 dir
= OHCI_BM(ed
->flags
, ED_D
);
507 case OHCI_TD_DIR_OUT
:
512 dir
= OHCI_BM(td
.flags
, TD_DP
);
521 case OHCI_TD_DIR_OUT
:
525 case OHCI_TD_DIR_SETUP
:
527 pid
= USB_TOKEN_SETUP
;
530 fprintf(stderr
, "usb-ohci: Bad direction\n");
533 if (td
.cbp
&& td
.be
) {
534 if ((td
.cbp
& 0xfffff000) != (td
.be
& 0xfffff000)) {
535 len
= (td
.be
& 0xfff) + 0x1001 - (td
.cbp
& 0xfff);
537 len
= (td
.be
- td
.cbp
) + 1;
540 if (len
&& dir
!= OHCI_TD_DIR_IN
&& !completion
) {
541 ohci_copy_td(&td
, ohci
->usb_buf
, len
, 0);
545 flag_r
= (td
.flags
& OHCI_TD_R
) != 0;
547 dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
548 addr
, len
, str
, flag_r
, td
.cbp
, td
.be
);
550 if (len
>= 0 && dir
!= OHCI_TD_DIR_IN
) {
552 for (i
= 0; i
< len
; i
++)
553 printf(" %.2x", ohci
->usb_buf
[i
]);
558 ret
= ohci
->usb_packet
.len
;
560 ohci
->async_complete
= 0;
563 for (i
= 0; i
< ohci
->num_ports
; i
++) {
564 dev
= ohci
->rhport
[i
].port
.dev
;
565 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0)
568 if (ohci
->async_td
) {
569 /* ??? The hardware should allow one active packet per
570 endpoint. We only allow one active packet per controller.
571 This should be sufficient as long as devices respond in a
575 dprintf("Too many pending packets\n");
579 ohci
->usb_packet
.pid
= pid
;
580 ohci
->usb_packet
.devaddr
= OHCI_BM(ed
->flags
, ED_FA
);
581 ohci
->usb_packet
.devep
= OHCI_BM(ed
->flags
, ED_EN
);
582 ohci
->usb_packet
.data
= ohci
->usb_buf
;
583 ohci
->usb_packet
.len
= len
;
584 ohci
->usb_packet
.complete_cb
= ohci_async_complete_packet
;
585 ohci
->usb_packet
.complete_opaque
= ohci
;
586 ret
= dev
->handle_packet(dev
, &ohci
->usb_packet
);
587 if (ret
!= USB_RET_NODEV
)
591 dprintf("ret=%d\n", ret
);
593 if (ret
== USB_RET_ASYNC
) {
594 ohci
->async_td
= addr
;
599 if (dir
== OHCI_TD_DIR_IN
) {
600 ohci_copy_td(&td
, ohci
->usb_buf
, ret
, 1);
603 for (i
= 0; i
< ret
; i
++)
604 printf(" %.2x", ohci
->usb_buf
[i
]);
613 if (ret
== len
|| (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && flag_r
)) {
614 /* Transmission succeeded. */
619 if ((td
.cbp
& 0xfff) + ret
> 0xfff) {
621 td
.cbp
|= td
.be
& ~0xfff;
624 td
.flags
|= OHCI_TD_T1
;
625 td
.flags
^= OHCI_TD_T0
;
626 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
627 OHCI_SET_BM(td
.flags
, TD_EC
, 0);
629 ed
->head
&= ~OHCI_ED_C
;
630 if (td
.flags
& OHCI_TD_T0
)
631 ed
->head
|= OHCI_ED_C
;
634 dprintf("usb-ohci: Underrun\n");
635 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAUNDERRUN
);
639 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DEVICENOTRESPONDING
);
641 dprintf("usb-ohci: got NAK\n");
644 dprintf("usb-ohci: got STALL\n");
645 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_STALL
);
648 dprintf("usb-ohci: got BABBLE\n");
649 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
652 fprintf(stderr
, "usb-ohci: Bad device response %d\n", ret
);
653 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_UNDEXPETEDPID
);
654 OHCI_SET_BM(td
.flags
, TD_EC
, 3);
658 ed
->head
|= OHCI_ED_H
;
662 ed
->head
&= ~OHCI_DPTR_MASK
;
663 ed
->head
|= td
.next
& OHCI_DPTR_MASK
;
664 td
.next
= ohci
->done
;
666 i
= OHCI_BM(td
.flags
, TD_DI
);
667 if (i
< ohci
->done_count
)
668 ohci
->done_count
= i
;
669 ohci_put_td(addr
, &td
);
670 return OHCI_BM(td
.flags
, TD_CC
) != OHCI_CC_NOERROR
;
673 /* Service an endpoint list. Returns nonzero if active TD were found. */
674 static int ohci_service_ed_list(OHCIState
*ohci
, uint32_t head
)
686 for (cur
= head
; cur
; cur
= next_ed
) {
687 if (!ohci_read_ed(cur
, &ed
)) {
688 fprintf(stderr
, "usb-ohci: ED read error at %x\n", cur
);
692 next_ed
= ed
.next
& OHCI_DPTR_MASK
;
694 if ((ed
.head
& OHCI_ED_H
) || (ed
.flags
& OHCI_ED_K
)) {
696 /* Cancel pending packets for ED that have been paused. */
697 addr
= ed
.head
& OHCI_DPTR_MASK
;
698 if (ohci
->async_td
&& addr
== ohci
->async_td
) {
699 usb_cancel_packet(&ohci
->usb_packet
);
705 /* Skip isochronous endpoints. */
706 if (ed
.flags
& OHCI_ED_F
)
709 while ((ed
.head
& OHCI_DPTR_MASK
) != ed
.tail
) {
711 dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
712 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur
,
713 OHCI_BM(ed
.flags
, ED_FA
), OHCI_BM(ed
.flags
, ED_EN
),
714 OHCI_BM(ed
.flags
, ED_D
), (ed
.flags
& OHCI_ED_S
)!= 0,
715 (ed
.flags
& OHCI_ED_K
) != 0, (ed
.flags
& OHCI_ED_F
) != 0,
716 OHCI_BM(ed
.flags
, ED_MPS
), (ed
.head
& OHCI_ED_H
) != 0,
717 (ed
.head
& OHCI_ED_C
) != 0, ed
.head
& OHCI_DPTR_MASK
,
718 ed
.tail
& OHCI_DPTR_MASK
, ed
.next
& OHCI_DPTR_MASK
);
722 if (ohci_service_td(ohci
, &ed
))
726 ohci_put_ed(cur
, &ed
);
732 /* Generate a SOF event, and set a timer for EOF */
733 static void ohci_sof(OHCIState
*ohci
)
735 ohci
->sof_time
= qemu_get_clock(vm_clock
);
736 qemu_mod_timer(ohci
->eof_timer
, ohci
->sof_time
+ usb_frame_time
);
737 ohci_set_interrupt(ohci
, OHCI_INTR_SF
);
740 /* Process Control and Bulk lists. */
741 static void ohci_process_lists(OHCIState
*ohci
)
743 if ((ohci
->ctl
& OHCI_CTL_CLE
) && (ohci
->status
& OHCI_STATUS_CLF
)) {
744 if (ohci
->ctrl_cur
&& ohci
->ctrl_cur
!= ohci
->ctrl_head
)
745 dprintf("usb-ohci: head %x, cur %x\n", ohci
->ctrl_head
, ohci
->ctrl_cur
);
746 if (!ohci_service_ed_list(ohci
, ohci
->ctrl_head
)) {
748 ohci
->status
&= ~OHCI_STATUS_CLF
;
752 if ((ohci
->ctl
& OHCI_CTL_BLE
) && (ohci
->status
& OHCI_STATUS_BLF
)) {
753 if (!ohci_service_ed_list(ohci
, ohci
->bulk_head
)) {
755 ohci
->status
&= ~OHCI_STATUS_BLF
;
760 /* Do frame processing on frame boundary */
761 static void ohci_frame_boundary(void *opaque
)
763 OHCIState
*ohci
= opaque
;
764 struct ohci_hcca hcca
;
766 cpu_physical_memory_rw(ohci
->hcca
, (uint8_t *)&hcca
, sizeof(hcca
), 0);
768 /* Process all the lists at the end of the frame */
769 if (ohci
->ctl
& OHCI_CTL_PLE
) {
772 n
= ohci
->frame_number
& 0x1f;
773 ohci_service_ed_list(ohci
, le32_to_cpu(hcca
.intr
[n
]));
776 /* Cancel all pending packets if either of the lists has been disabled. */
777 if (ohci
->async_td
&&
778 ohci
->old_ctl
& (~ohci
->ctl
) & (OHCI_CTL_BLE
| OHCI_CTL_CLE
)) {
779 usb_cancel_packet(&ohci
->usb_packet
);
782 ohci
->old_ctl
= ohci
->ctl
;
783 ohci_process_lists(ohci
);
785 /* Frame boundary, so do EOF stuf here */
786 ohci
->frt
= ohci
->fit
;
788 /* XXX: endianness */
789 ohci
->frame_number
= (ohci
->frame_number
+ 1) & 0xffff;
790 hcca
.frame
= cpu_to_le32(ohci
->frame_number
);
792 if (ohci
->done_count
== 0 && !(ohci
->intr_status
& OHCI_INTR_WD
)) {
795 if (ohci
->intr
& ohci
->intr_status
)
797 hcca
.done
= cpu_to_le32(ohci
->done
);
799 ohci
->done_count
= 7;
800 ohci_set_interrupt(ohci
, OHCI_INTR_WD
);
803 if (ohci
->done_count
!= 7 && ohci
->done_count
!= 0)
806 /* Do SOF stuff here */
810 cpu_physical_memory_rw(ohci
->hcca
, (uint8_t *)&hcca
, sizeof(hcca
), 1);
813 /* Start sending SOF tokens across the USB bus, lists are processed in
816 static int ohci_bus_start(OHCIState
*ohci
)
818 ohci
->eof_timer
= qemu_new_timer(vm_clock
,
822 if (ohci
->eof_timer
== NULL
) {
823 fprintf(stderr
, "usb-ohci: %s: qemu_new_timer failed\n", ohci
->name
);
824 /* TODO: Signal unrecoverable error */
828 dprintf("usb-ohci: %s: USB Operational\n", ohci
->name
);
835 /* Stop sending SOF tokens on the bus */
836 static void ohci_bus_stop(OHCIState
*ohci
)
839 qemu_del_timer(ohci
->eof_timer
);
842 /* Sets a flag in a port status register but only set it if the port is
843 * connected, if not set ConnectStatusChange flag. If flag is enabled
846 static int ohci_port_set_if_connected(OHCIState
*ohci
, int i
, uint32_t val
)
850 /* writing a 0 has no effect */
854 /* If CurrentConnectStatus is cleared we set
855 * ConnectStatusChange
857 if (!(ohci
->rhport
[i
].ctrl
& OHCI_PORT_CCS
)) {
858 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_CSC
;
859 if (ohci
->rhstatus
& OHCI_RHS_DRWE
) {
860 /* TODO: CSC is a wakeup event */
865 if (ohci
->rhport
[i
].ctrl
& val
)
869 ohci
->rhport
[i
].ctrl
|= val
;
874 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
875 static void ohci_set_frame_interval(OHCIState
*ohci
, uint16_t val
)
879 if (val
!= ohci
->fi
) {
880 dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
881 ohci
->name
, ohci
->fi
, ohci
->fi
);
887 static void ohci_port_power(OHCIState
*ohci
, int i
, int p
)
890 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_PPS
;
892 ohci
->rhport
[i
].ctrl
&= ~(OHCI_PORT_PPS
|
899 /* Set HcControlRegister */
900 static void ohci_set_ctl(OHCIState
*ohci
, uint32_t val
)
905 old_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
907 new_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
909 /* no state change */
910 if (old_state
== new_state
)
914 case OHCI_USB_OPERATIONAL
:
915 ohci_bus_start(ohci
);
917 case OHCI_USB_SUSPEND
:
919 dprintf("usb-ohci: %s: USB Suspended\n", ohci
->name
);
921 case OHCI_USB_RESUME
:
922 dprintf("usb-ohci: %s: USB Resume\n", ohci
->name
);
925 dprintf("usb-ohci: %s: USB Reset\n", ohci
->name
);
930 static uint32_t ohci_get_frame_remaining(OHCIState
*ohci
)
935 if ((ohci
->ctl
& OHCI_CTL_HCFS
) != OHCI_USB_OPERATIONAL
)
936 return (ohci
->frt
<< 31);
938 /* Being in USB operational state guarnatees sof_time was
941 tks
= qemu_get_clock(vm_clock
) - ohci
->sof_time
;
943 /* avoid muldiv if possible */
944 if (tks
>= usb_frame_time
)
945 return (ohci
->frt
<< 31);
947 tks
= muldiv64(1, tks
, usb_bit_time
);
948 fr
= (uint16_t)(ohci
->fi
- tks
);
950 return (ohci
->frt
<< 31) | fr
;
954 /* Set root hub status */
955 static void ohci_set_hub_status(OHCIState
*ohci
, uint32_t val
)
959 old_state
= ohci
->rhstatus
;
961 /* write 1 to clear OCIC */
962 if (val
& OHCI_RHS_OCIC
)
963 ohci
->rhstatus
&= ~OHCI_RHS_OCIC
;
965 if (val
& OHCI_RHS_LPS
) {
968 for (i
= 0; i
< ohci
->num_ports
; i
++)
969 ohci_port_power(ohci
, i
, 0);
970 dprintf("usb-ohci: powered down all ports\n");
973 if (val
& OHCI_RHS_LPSC
) {
976 for (i
= 0; i
< ohci
->num_ports
; i
++)
977 ohci_port_power(ohci
, i
, 1);
978 dprintf("usb-ohci: powered up all ports\n");
981 if (val
& OHCI_RHS_DRWE
)
982 ohci
->rhstatus
|= OHCI_RHS_DRWE
;
984 if (val
& OHCI_RHS_CRWE
)
985 ohci
->rhstatus
&= ~OHCI_RHS_DRWE
;
987 if (old_state
!= ohci
->rhstatus
)
988 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
991 /* Set root hub port status */
992 static void ohci_port_set_status(OHCIState
*ohci
, int portnum
, uint32_t val
)
997 port
= &ohci
->rhport
[portnum
];
998 old_state
= port
->ctrl
;
1000 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1001 if (val
& OHCI_PORT_WTC
)
1002 port
->ctrl
&= ~(val
& OHCI_PORT_WTC
);
1004 if (val
& OHCI_PORT_CCS
)
1005 port
->ctrl
&= ~OHCI_PORT_PES
;
1007 ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PES
);
1009 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PSS
))
1010 dprintf("usb-ohci: port %d: SUSPEND\n", portnum
);
1012 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PRS
)) {
1013 dprintf("usb-ohci: port %d: RESET\n", portnum
);
1014 usb_send_msg(port
->port
.dev
, USB_MSG_RESET
);
1015 port
->ctrl
&= ~OHCI_PORT_PRS
;
1016 /* ??? Should this also set OHCI_PORT_PESC. */
1017 port
->ctrl
|= OHCI_PORT_PES
| OHCI_PORT_PRSC
;
1020 /* Invert order here to ensure in ambiguous case, device is
1023 if (val
& OHCI_PORT_LSDA
)
1024 ohci_port_power(ohci
, portnum
, 0);
1025 if (val
& OHCI_PORT_PPS
)
1026 ohci_port_power(ohci
, portnum
, 1);
1028 if (old_state
!= port
->ctrl
)
1029 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1034 static uint32_t ohci_mem_read(void *ptr
, target_phys_addr_t addr
)
1036 OHCIState
*ohci
= ptr
;
1038 addr
-= ohci
->mem_base
;
1040 /* Only aligned reads are allowed on OHCI */
1042 fprintf(stderr
, "usb-ohci: Mis-aligned read\n");
1046 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1047 /* HcRhPortStatus */
1048 return ohci
->rhport
[(addr
- 0x54) >> 2].ctrl
| OHCI_PORT_PPS
;
1051 switch (addr
>> 2) {
1052 case 0: /* HcRevision */
1055 case 1: /* HcControl */
1058 case 2: /* HcCommandStatus */
1059 return ohci
->status
;
1061 case 3: /* HcInterruptStatus */
1062 return ohci
->intr_status
;
1064 case 4: /* HcInterruptEnable */
1065 case 5: /* HcInterruptDisable */
1068 case 6: /* HcHCCA */
1071 case 7: /* HcPeriodCurrentED */
1072 return ohci
->per_cur
;
1074 case 8: /* HcControlHeadED */
1075 return ohci
->ctrl_head
;
1077 case 9: /* HcControlCurrentED */
1078 return ohci
->ctrl_cur
;
1080 case 10: /* HcBulkHeadED */
1081 return ohci
->bulk_head
;
1083 case 11: /* HcBulkCurrentED */
1084 return ohci
->bulk_cur
;
1086 case 12: /* HcDoneHead */
1089 case 13: /* HcFmInterval */
1090 return (ohci
->fit
<< 31) | (ohci
->fsmps
<< 16) | (ohci
->fi
);
1092 case 14: /* HcFmRemaining */
1093 return ohci_get_frame_remaining(ohci
);
1095 case 15: /* HcFmNumber */
1096 return ohci
->frame_number
;
1098 case 16: /* HcPeriodicStart */
1099 return ohci
->pstart
;
1101 case 17: /* HcLSThreshold */
1104 case 18: /* HcRhDescriptorA */
1105 return ohci
->rhdesc_a
;
1107 case 19: /* HcRhDescriptorB */
1108 return ohci
->rhdesc_b
;
1110 case 20: /* HcRhStatus */
1111 return ohci
->rhstatus
;
1113 /* PXA27x specific registers */
1114 case 24: /* HcStatus */
1115 return ohci
->hstatus
& ohci
->hmask
;
1117 case 25: /* HcHReset */
1118 return ohci
->hreset
;
1120 case 26: /* HcHInterruptEnable */
1123 case 27: /* HcHInterruptTest */
1127 fprintf(stderr
, "ohci_read: Bad offset %x\n", (int)addr
);
1132 static void ohci_mem_write(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1134 OHCIState
*ohci
= ptr
;
1136 addr
-= ohci
->mem_base
;
1138 /* Only aligned reads are allowed on OHCI */
1140 fprintf(stderr
, "usb-ohci: Mis-aligned write\n");
1144 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1145 /* HcRhPortStatus */
1146 ohci_port_set_status(ohci
, (addr
- 0x54) >> 2, val
);
1150 switch (addr
>> 2) {
1151 case 1: /* HcControl */
1152 ohci_set_ctl(ohci
, val
);
1155 case 2: /* HcCommandStatus */
1156 /* SOC is read-only */
1157 val
= (val
& ~OHCI_STATUS_SOC
);
1159 /* Bits written as '0' remain unchanged in the register */
1160 ohci
->status
|= val
;
1162 if (ohci
->status
& OHCI_STATUS_HCR
)
1166 case 3: /* HcInterruptStatus */
1167 ohci
->intr_status
&= ~val
;
1168 ohci_intr_update(ohci
);
1171 case 4: /* HcInterruptEnable */
1173 ohci_intr_update(ohci
);
1176 case 5: /* HcInterruptDisable */
1178 ohci_intr_update(ohci
);
1181 case 6: /* HcHCCA */
1182 ohci
->hcca
= val
& OHCI_HCCA_MASK
;
1185 case 8: /* HcControlHeadED */
1186 ohci
->ctrl_head
= val
& OHCI_EDPTR_MASK
;
1189 case 9: /* HcControlCurrentED */
1190 ohci
->ctrl_cur
= val
& OHCI_EDPTR_MASK
;
1193 case 10: /* HcBulkHeadED */
1194 ohci
->bulk_head
= val
& OHCI_EDPTR_MASK
;
1197 case 11: /* HcBulkCurrentED */
1198 ohci
->bulk_cur
= val
& OHCI_EDPTR_MASK
;
1201 case 13: /* HcFmInterval */
1202 ohci
->fsmps
= (val
& OHCI_FMI_FSMPS
) >> 16;
1203 ohci
->fit
= (val
& OHCI_FMI_FIT
) >> 31;
1204 ohci_set_frame_interval(ohci
, val
);
1207 case 16: /* HcPeriodicStart */
1208 ohci
->pstart
= val
& 0xffff;
1211 case 17: /* HcLSThreshold */
1212 ohci
->lst
= val
& 0xffff;
1215 case 18: /* HcRhDescriptorA */
1216 ohci
->rhdesc_a
&= ~OHCI_RHA_RW_MASK
;
1217 ohci
->rhdesc_a
|= val
& OHCI_RHA_RW_MASK
;
1220 case 19: /* HcRhDescriptorB */
1223 case 20: /* HcRhStatus */
1224 ohci_set_hub_status(ohci
, val
);
1227 /* PXA27x specific registers */
1228 case 24: /* HcStatus */
1229 ohci
->hstatus
&= ~(val
& ohci
->hmask
);
1231 case 25: /* HcHReset */
1232 ohci
->hreset
= val
& ~OHCI_HRESET_FSBIR
;
1233 if (val
& OHCI_HRESET_FSBIR
)
1237 case 26: /* HcHInterruptEnable */
1241 case 27: /* HcHInterruptTest */
1246 fprintf(stderr
, "ohci_write: Bad offset %x\n", (int)addr
);
1251 /* Only dword reads are defined on OHCI register space */
1252 static CPUReadMemoryFunc
*ohci_readfn
[3]={
1258 /* Only dword writes are defined on OHCI register space */
1259 static CPUWriteMemoryFunc
*ohci_writefn
[3]={
1265 static void usb_ohci_init(OHCIState
*ohci
, int num_ports
, int devfn
,
1266 void *pic
, int irq
, enum ohci_type type
, const char *name
)
1270 if (usb_frame_time
== 0) {
1272 usb_frame_time
= ticks_per_sec
;
1273 usb_bit_time
= muldiv64(1, ticks_per_sec
, USB_HZ
/1000);
1275 usb_frame_time
= muldiv64(1, ticks_per_sec
, 1000);
1276 if (ticks_per_sec
>= USB_HZ
) {
1277 usb_bit_time
= muldiv64(1, ticks_per_sec
, USB_HZ
);
1282 dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
1283 usb_frame_time
, usb_bit_time
);
1286 ohci
->mem
= cpu_register_io_memory(0, ohci_readfn
, ohci_writefn
, ohci
);
1293 ohci
->num_ports
= num_ports
;
1294 for (i
= 0; i
< num_ports
; i
++) {
1295 qemu_register_usb_port(&ohci
->rhport
[i
].port
, ohci
, i
, ohci_attach
);
1307 static void ohci_mapfunc(PCIDevice
*pci_dev
, int i
,
1308 uint32_t addr
, uint32_t size
, int type
)
1310 OHCIPCIState
*ohci
= (OHCIPCIState
*)pci_dev
;
1311 ohci
->state
.mem_base
= addr
;
1312 cpu_register_physical_memory(addr
, size
, ohci
->state
.mem
);
1315 void usb_ohci_init_pci(struct PCIBus
*bus
, int num_ports
, int devfn
)
1321 ohci
= (OHCIPCIState
*)pci_register_device(bus
, "OHCI USB", sizeof(*ohci
),
1324 fprintf(stderr
, "usb-ohci: Failed to register PCI device\n");
1328 ohci
->pci_dev
.config
[0x00] = vid
& 0xff;
1329 ohci
->pci_dev
.config
[0x01] = (vid
>> 8) & 0xff;
1330 ohci
->pci_dev
.config
[0x02] = did
& 0xff;
1331 ohci
->pci_dev
.config
[0x03] = (did
>> 8) & 0xff;
1332 ohci
->pci_dev
.config
[0x09] = 0x10; /* OHCI */
1333 ohci
->pci_dev
.config
[0x0a] = 0x3;
1334 ohci
->pci_dev
.config
[0x0b] = 0xc;
1335 ohci
->pci_dev
.config
[0x3d] = 0x01; /* interrupt pin 1 */
1337 usb_ohci_init(&ohci
->state
, num_ports
, devfn
, &ohci
->pci_dev
,
1338 0, OHCI_TYPE_PCI
, ohci
->pci_dev
.name
);
1340 pci_register_io_region((struct PCIDevice
*)ohci
, 0, 256,
1341 PCI_ADDRESS_SPACE_MEM
, ohci_mapfunc
);
1344 void usb_ohci_init_pxa(target_phys_addr_t base
, int num_ports
, int devfn
,
1347 OHCIState
*ohci
= (OHCIState
*)qemu_mallocz(sizeof(OHCIState
));
1349 usb_ohci_init(ohci
, num_ports
, devfn
, pic
, irq
,
1350 OHCI_TYPE_PXA
, "OHCI USB");
1351 ohci
->mem_base
= base
;
1353 cpu_register_physical_memory(ohci
->mem_base
, 0xfff, ohci
->mem
);