4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 pci_set_irq_fn set_irq
;
32 uint32_t config_reg
; /* XXX: suppress */
34 SetIRQFunc
*low_set_irq
;
36 PCIDevice
*devices
[256];
39 target_phys_addr_t pci_mem_base
;
40 static int pci_irq_index
;
41 static PCIBus
*first_bus
;
43 PCIBus
*pci_register_bus(pci_set_irq_fn set_irq
, void *pic
, int devfn_min
)
46 bus
= qemu_mallocz(sizeof(PCIBus
));
47 bus
->set_irq
= set_irq
;
48 bus
->irq_opaque
= pic
;
49 bus
->devfn_min
= devfn_min
;
54 int pci_bus_num(PCIBus
*s
)
59 void generic_pci_save(QEMUFile
* f
, void *opaque
)
61 PCIDevice
* s
=(PCIDevice
*)opaque
;
63 qemu_put_buffer(f
, s
->config
, 256);
66 int generic_pci_load(QEMUFile
* f
, void *opaque
, int version_id
)
68 PCIDevice
* s
=(PCIDevice
*)opaque
;
73 qemu_get_buffer(f
, s
->config
, 256);
77 /* -1 for devfn means auto assign */
78 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
79 int instance_size
, int devfn
,
80 PCIConfigReadFunc
*config_read
,
81 PCIConfigWriteFunc
*config_write
)
85 if (pci_irq_index
>= PCI_DEVICES_MAX
)
89 for(devfn
= bus
->devfn_min
; devfn
< 256; devfn
+= 8) {
90 if (!bus
->devices
[devfn
])
96 pci_dev
= qemu_mallocz(instance_size
);
100 pci_dev
->devfn
= devfn
;
101 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
104 config_read
= pci_default_read_config
;
106 config_write
= pci_default_write_config
;
107 pci_dev
->config_read
= config_read
;
108 pci_dev
->config_write
= config_write
;
109 pci_dev
->irq_index
= pci_irq_index
++;
110 bus
->devices
[devfn
] = pci_dev
;
114 void pci_register_io_region(PCIDevice
*pci_dev
, int region_num
,
115 uint32_t size
, int type
,
116 PCIMapIORegionFunc
*map_func
)
121 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
123 r
= &pci_dev
->io_regions
[region_num
];
127 r
->map_func
= map_func
;
128 if (region_num
== PCI_ROM_SLOT
) {
131 addr
= 0x10 + region_num
* 4;
133 *(uint32_t *)(pci_dev
->config
+ addr
) = cpu_to_le32(type
);
136 target_phys_addr_t
pci_to_cpu_addr(target_phys_addr_t addr
)
138 return addr
+ pci_mem_base
;
141 static void pci_update_mappings(PCIDevice
*d
)
145 uint32_t last_addr
, new_addr
, config_ofs
;
147 cmd
= le16_to_cpu(*(uint16_t *)(d
->config
+ PCI_COMMAND
));
148 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
149 r
= &d
->io_regions
[i
];
150 if (i
== PCI_ROM_SLOT
) {
153 config_ofs
= 0x10 + i
* 4;
156 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
157 if (cmd
& PCI_COMMAND_IO
) {
158 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
160 new_addr
= new_addr
& ~(r
->size
- 1);
161 last_addr
= new_addr
+ r
->size
- 1;
162 /* NOTE: we have only 64K ioports on PC */
163 if (last_addr
<= new_addr
|| new_addr
== 0 ||
164 last_addr
>= 0x10000) {
171 if (cmd
& PCI_COMMAND_MEMORY
) {
172 new_addr
= le32_to_cpu(*(uint32_t *)(d
->config
+
174 /* the ROM slot has a specific enable bit */
175 if (i
== PCI_ROM_SLOT
&& !(new_addr
& 1))
177 new_addr
= new_addr
& ~(r
->size
- 1);
178 last_addr
= new_addr
+ r
->size
- 1;
179 /* NOTE: we do not support wrapping */
180 /* XXX: as we cannot support really dynamic
181 mappings, we handle specific values as invalid
183 if (last_addr
<= new_addr
|| new_addr
== 0 ||
192 /* now do the real mapping */
193 if (new_addr
!= r
->addr
) {
195 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
197 /* NOTE: specific hack for IDE in PC case:
198 only one byte must be mapped. */
199 class = d
->config
[0x0a] | (d
->config
[0x0b] << 8);
200 if (class == 0x0101 && r
->size
== 4) {
201 isa_unassign_ioport(r
->addr
+ 2, 1);
203 isa_unassign_ioport(r
->addr
, r
->size
);
206 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
213 r
->map_func(d
, i
, r
->addr
, r
->size
, r
->type
);
220 uint32_t pci_default_read_config(PCIDevice
*d
,
221 uint32_t address
, int len
)
226 val
= d
->config
[address
];
229 val
= le16_to_cpu(*(uint16_t *)(d
->config
+ address
));
233 val
= le32_to_cpu(*(uint32_t *)(d
->config
+ address
));
239 void pci_default_write_config(PCIDevice
*d
,
240 uint32_t address
, uint32_t val
, int len
)
245 if (len
== 4 && ((address
>= 0x10 && address
< 0x10 + 4 * 6) ||
246 (address
>= 0x30 && address
< 0x34))) {
250 if ( address
>= 0x30 ) {
253 reg
= (address
- 0x10) >> 2;
255 r
= &d
->io_regions
[reg
];
258 /* compute the stored value */
259 if (reg
== PCI_ROM_SLOT
) {
260 /* keep ROM enable bit */
261 val
&= (~(r
->size
- 1)) | 1;
263 val
&= ~(r
->size
- 1);
266 *(uint32_t *)(d
->config
+ address
) = cpu_to_le32(val
);
267 pci_update_mappings(d
);
271 /* not efficient, but simple */
273 for(i
= 0; i
< len
; i
++) {
274 /* default read/write accesses */
275 switch(d
->config
[0x0e]) {
288 case 0x10 ... 0x27: /* base */
289 case 0x30 ... 0x33: /* rom */
310 case 0x38 ... 0x3b: /* rom */
321 d
->config
[addr
] = val
;
328 if (end
> PCI_COMMAND
&& address
< (PCI_COMMAND
+ 2)) {
329 /* if the command register is modified, we must modify the mappings */
330 pci_update_mappings(d
);
334 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
)
338 int config_addr
, bus_num
;
340 #if defined(DEBUG_PCI) && 0
341 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
344 bus_num
= (addr
>> 16) & 0xff;
347 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
350 config_addr
= addr
& 0xff;
351 #if defined(DEBUG_PCI)
352 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
353 pci_dev
->name
, config_addr
, val
, len
);
355 pci_dev
->config_write(pci_dev
, config_addr
, val
, len
);
358 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
)
362 int config_addr
, bus_num
;
365 bus_num
= (addr
>> 16) & 0xff;
368 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
385 config_addr
= addr
& 0xff;
386 val
= pci_dev
->config_read(pci_dev
, config_addr
, len
);
387 #if defined(DEBUG_PCI)
388 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
389 pci_dev
->name
, config_addr
, val
, len
);
392 #if defined(DEBUG_PCI) && 0
393 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
399 /***********************************************************/
400 /* generic PCI irq support */
402 /* 0 <= irq_num <= 3. level must be 0 or 1 */
403 void pci_set_irq(PCIDevice
*pci_dev
, int irq_num
, int level
)
405 PCIBus
*bus
= pci_dev
->bus
;
406 bus
->set_irq(pci_dev
, bus
->irq_opaque
, irq_num
, level
);
409 /***********************************************************/
410 /* monitor info on PCI */
417 static pci_class_desc pci_class_descriptions
[] =
419 { 0x0101, "IDE controller"},
420 { 0x0200, "Ethernet controller"},
421 { 0x0300, "VGA controller"},
422 { 0x0600, "Host bridge"},
423 { 0x0601, "ISA bridge"},
424 { 0x0604, "PCI bridge"},
425 { 0x0c03, "USB controller"},
429 static void pci_info_device(PCIDevice
*d
)
433 pci_class_desc
*desc
;
435 term_printf(" Bus %2d, device %3d, function %d:\n",
436 d
->bus
->bus_num
, d
->devfn
>> 3, d
->devfn
& 7);
437 class = le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_CLASS_DEVICE
)));
439 desc
= pci_class_descriptions
;
440 while (desc
->desc
&& class != desc
->class)
443 term_printf("%s", desc
->desc
);
445 term_printf("Class %04x", class);
447 term_printf(": PCI device %04x:%04x\n",
448 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_VENDOR_ID
))),
449 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_DEVICE_ID
))));
451 if (d
->config
[PCI_INTERRUPT_PIN
] != 0) {
452 term_printf(" IRQ %d.\n", d
->config
[PCI_INTERRUPT_LINE
]);
454 for(i
= 0;i
< PCI_NUM_REGIONS
; i
++) {
455 r
= &d
->io_regions
[i
];
457 term_printf(" BAR%d: ", i
);
458 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
459 term_printf("I/O at 0x%04x [0x%04x].\n",
460 r
->addr
, r
->addr
+ r
->size
- 1);
462 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
463 r
->addr
, r
->addr
+ r
->size
- 1);
469 void pci_for_each_device(void (*fn
)(PCIDevice
*d
))
471 PCIBus
*bus
= first_bus
;
476 for(devfn
= 0; devfn
< 256; devfn
++) {
477 d
= bus
->devices
[devfn
];
486 pci_for_each_device(pci_info_device
);
489 /* Initialize a PCI NIC. */
490 void pci_nic_init(PCIBus
*bus
, NICInfo
*nd
)
492 if (strcmp(nd
->model
, "ne2k_pci") == 0) {
493 pci_ne2000_init(bus
, nd
);
494 } else if (strcmp(nd
->model
, "rtl8139") == 0) {
495 pci_rtl8139_init(bus
, nd
);
497 fprintf(stderr
, "qemu: Unsupported NIC: %s\n", nd
->model
);