2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), also
31 * produced as NCR89C100. See
32 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
38 #define DPRINTF(fmt, args...) \
39 do { printf("ESP: " fmt , ##args); } while (0)
41 #define DPRINTF(fmt, args...)
46 #define ESP_SIZE (ESP_REGS * 4)
48 /* The HBA is ID 7, so for simplicitly limit to 7 devices. */
49 #define ESP_MAX_DEVS 7
51 typedef struct ESPState ESPState
;
55 BlockDriverState
**bd
;
56 uint8_t rregs
[ESP_REGS
];
57 uint8_t wregs
[ESP_REGS
];
59 uint32_t ti_rptr
, ti_wptr
;
60 uint8_t ti_buf
[TI_BUFSZ
];
63 SCSIDevice
*scsi_dev
[MAX_DISKS
];
64 SCSIDevice
*current_dev
;
65 uint8_t cmdbuf
[TI_BUFSZ
];
69 /* The amount of data left in the current DMA transfer. */
71 /* The size of the current DMA transfer. Zero if no transfer is in
99 static int get_cmd(ESPState
*s
, uint8_t *buf
)
104 dmalen
= s
->rregs
[0] | (s
->rregs
[1] << 8);
105 target
= s
->wregs
[4] & 7;
106 DPRINTF("get_cmd: len %d target %d\n", dmalen
, target
);
108 espdma_memory_read(s
->dma_opaque
, buf
, dmalen
);
111 memcpy(&buf
[1], s
->ti_buf
, dmalen
);
119 if (s
->current_dev
) {
120 /* Started a new command before the old one finished. Cancel it. */
121 scsi_cancel_io(s
->current_dev
, 0);
125 if (target
>= MAX_DISKS
|| !s
->scsi_dev
[target
]) {
127 s
->rregs
[4] = STAT_IN
;
128 s
->rregs
[5] = INTR_DC
;
130 qemu_irq_raise(s
->irq
);
133 s
->current_dev
= s
->scsi_dev
[target
];
137 static void do_cmd(ESPState
*s
, uint8_t *buf
)
142 DPRINTF("do_cmd: busid 0x%x\n", buf
[0]);
144 datalen
= scsi_send_command(s
->current_dev
, 0, &buf
[1], lun
);
145 s
->ti_size
= datalen
;
147 s
->rregs
[4] = STAT_IN
| STAT_TC
;
151 s
->rregs
[4] |= STAT_DI
;
152 scsi_read_data(s
->current_dev
, 0);
154 s
->rregs
[4] |= STAT_DO
;
155 scsi_write_data(s
->current_dev
, 0);
158 s
->rregs
[5] = INTR_BS
| INTR_FC
;
159 s
->rregs
[6] = SEQ_CD
;
160 qemu_irq_raise(s
->irq
);
163 static void handle_satn(ESPState
*s
)
168 len
= get_cmd(s
, buf
);
173 static void handle_satn_stop(ESPState
*s
)
175 s
->cmdlen
= get_cmd(s
, s
->cmdbuf
);
177 DPRINTF("Set ATN & Stop: cmdlen %d\n", s
->cmdlen
);
179 s
->rregs
[4] = STAT_IN
| STAT_TC
| STAT_CD
;
180 s
->rregs
[5] = INTR_BS
| INTR_FC
;
181 s
->rregs
[6] = SEQ_CD
;
182 qemu_irq_raise(s
->irq
);
186 static void write_response(ESPState
*s
)
188 DPRINTF("Transfer status (sense=%d)\n", s
->sense
);
189 s
->ti_buf
[0] = s
->sense
;
192 espdma_memory_write(s
->dma_opaque
, s
->ti_buf
, 2);
193 s
->rregs
[4] = STAT_IN
| STAT_TC
| STAT_ST
;
194 s
->rregs
[5] = INTR_BS
| INTR_FC
;
195 s
->rregs
[6] = SEQ_CD
;
202 qemu_irq_raise(s
->irq
);
205 static void esp_dma_done(ESPState
*s
)
207 s
->rregs
[4] |= STAT_IN
| STAT_TC
;
208 s
->rregs
[5] = INTR_BS
;
213 qemu_irq_raise(s
->irq
);
216 static void esp_do_dma(ESPState
*s
)
221 to_device
= (s
->ti_size
< 0);
224 DPRINTF("command len %d + %d\n", s
->cmdlen
, len
);
225 espdma_memory_read(s
->dma_opaque
, &s
->cmdbuf
[s
->cmdlen
], len
);
229 do_cmd(s
, s
->cmdbuf
);
232 if (s
->async_len
== 0) {
233 /* Defer until data is available. */
236 if (len
> s
->async_len
) {
240 espdma_memory_read(s
->dma_opaque
, s
->async_buf
, len
);
242 espdma_memory_write(s
->dma_opaque
, s
->async_buf
, len
);
251 if (s
->async_len
== 0) {
253 // ti_size is negative
254 scsi_write_data(s
->current_dev
, 0);
256 scsi_read_data(s
->current_dev
, 0);
257 /* If there is still data to be read from the device then
258 complete the DMA operation immeriately. Otherwise defer
259 until the scsi layer has completed. */
260 if (s
->dma_left
== 0 && s
->ti_size
> 0) {
265 /* Partially filled a scsi buffer. Complete immediately. */
270 static void esp_command_complete(void *opaque
, int reason
, uint32_t tag
,
273 ESPState
*s
= (ESPState
*)opaque
;
275 if (reason
== SCSI_REASON_DONE
) {
276 DPRINTF("SCSI Command complete\n");
278 DPRINTF("SCSI command completed unexpectedly\n");
283 DPRINTF("Command failed\n");
285 s
->rregs
[4] = STAT_ST
;
287 s
->current_dev
= NULL
;
289 DPRINTF("transfer %d/%d\n", s
->dma_left
, s
->ti_size
);
291 s
->async_buf
= scsi_get_buf(s
->current_dev
, 0);
294 } else if (s
->dma_counter
!= 0 && s
->ti_size
<= 0) {
295 /* If this was the last part of a DMA transfer then the
296 completion interrupt is deferred to here. */
302 static void handle_ti(ESPState
*s
)
304 uint32_t dmalen
, minlen
;
306 dmalen
= s
->rregs
[0] | (s
->rregs
[1] << 8);
310 s
->dma_counter
= dmalen
;
313 minlen
= (dmalen
< 32) ? dmalen
: 32;
314 else if (s
->ti_size
< 0)
315 minlen
= (dmalen
< -s
->ti_size
) ? dmalen
: -s
->ti_size
;
317 minlen
= (dmalen
< s
->ti_size
) ? dmalen
: s
->ti_size
;
318 DPRINTF("Transfer Information len %d\n", minlen
);
320 s
->dma_left
= minlen
;
321 s
->rregs
[4] &= ~STAT_TC
;
323 } else if (s
->do_cmd
) {
324 DPRINTF("command len %d\n", s
->cmdlen
);
328 do_cmd(s
, s
->cmdbuf
);
333 static void esp_reset(void *opaque
)
335 ESPState
*s
= opaque
;
337 memset(s
->rregs
, 0, ESP_REGS
);
338 memset(s
->wregs
, 0, ESP_REGS
);
339 s
->rregs
[0x0e] = 0x4; // Indicate fas100a
347 static uint32_t esp_mem_readb(void *opaque
, target_phys_addr_t addr
)
349 ESPState
*s
= opaque
;
352 saddr
= (addr
& ESP_MASK
) >> 2;
353 DPRINTF("read reg[%d]: 0x%2.2x\n", saddr
, s
->rregs
[saddr
]);
357 if (s
->ti_size
> 0) {
359 if ((s
->rregs
[4] & 6) == 0) {
361 fprintf(stderr
, "esp: PIO data read not implemented\n");
364 s
->rregs
[2] = s
->ti_buf
[s
->ti_rptr
++];
366 qemu_irq_raise(s
->irq
);
368 if (s
->ti_size
== 0) {
375 // Clear interrupt/error status bits
376 s
->rregs
[4] &= ~(STAT_IN
| STAT_GE
| STAT_PE
);
377 qemu_irq_lower(s
->irq
);
382 return s
->rregs
[saddr
];
385 static void esp_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
387 ESPState
*s
= opaque
;
390 saddr
= (addr
& ESP_MASK
) >> 2;
391 DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr
, s
->wregs
[saddr
], val
);
395 s
->rregs
[4] &= ~STAT_TC
;
400 s
->cmdbuf
[s
->cmdlen
++] = val
& 0xff;
401 } else if ((s
->rregs
[4] & 6) == 0) {
405 fprintf(stderr
, "esp: PIO data write not implemented\n");
408 s
->ti_buf
[s
->ti_wptr
++] = val
& 0xff;
412 s
->rregs
[saddr
] = val
;
416 /* Reload DMA counter. */
417 s
->rregs
[0] = s
->wregs
[0];
418 s
->rregs
[1] = s
->wregs
[1];
424 DPRINTF("NOP (%2.2x)\n", val
);
427 DPRINTF("Flush FIFO (%2.2x)\n", val
);
429 s
->rregs
[5] = INTR_FC
;
433 DPRINTF("Chip reset (%2.2x)\n", val
);
437 DPRINTF("Bus reset (%2.2x)\n", val
);
438 s
->rregs
[5] = INTR_RST
;
439 if (!(s
->wregs
[8] & 0x40)) {
440 qemu_irq_raise(s
->irq
);
447 DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val
);
451 DPRINTF("Message Accepted (%2.2x)\n", val
);
453 s
->rregs
[5] = INTR_DC
;
457 DPRINTF("Set ATN (%2.2x)\n", val
);
460 DPRINTF("Set ATN (%2.2x)\n", val
);
464 DPRINTF("Set ATN & stop (%2.2x)\n", val
);
468 DPRINTF("Unhandled ESP command (%2.2x)\n", val
);
475 s
->rregs
[saddr
] = val
;
480 s
->rregs
[saddr
] = val
& 0x15;
483 s
->rregs
[saddr
] = val
;
488 s
->wregs
[saddr
] = val
;
491 static CPUReadMemoryFunc
*esp_mem_read
[3] = {
497 static CPUWriteMemoryFunc
*esp_mem_write
[3] = {
503 static void esp_save(QEMUFile
*f
, void *opaque
)
505 ESPState
*s
= opaque
;
507 qemu_put_buffer(f
, s
->rregs
, ESP_REGS
);
508 qemu_put_buffer(f
, s
->wregs
, ESP_REGS
);
509 qemu_put_be32s(f
, &s
->ti_size
);
510 qemu_put_be32s(f
, &s
->ti_rptr
);
511 qemu_put_be32s(f
, &s
->ti_wptr
);
512 qemu_put_buffer(f
, s
->ti_buf
, TI_BUFSZ
);
513 qemu_put_be32s(f
, &s
->sense
);
514 qemu_put_be32s(f
, &s
->dma
);
515 qemu_put_buffer(f
, s
->cmdbuf
, TI_BUFSZ
);
516 qemu_put_be32s(f
, &s
->cmdlen
);
517 qemu_put_be32s(f
, &s
->do_cmd
);
518 qemu_put_be32s(f
, &s
->dma_left
);
519 // There should be no transfers in progress, so dma_counter is not saved
522 static int esp_load(QEMUFile
*f
, void *opaque
, int version_id
)
524 ESPState
*s
= opaque
;
527 return -EINVAL
; // Cannot emulate 2
529 qemu_get_buffer(f
, s
->rregs
, ESP_REGS
);
530 qemu_get_buffer(f
, s
->wregs
, ESP_REGS
);
531 qemu_get_be32s(f
, &s
->ti_size
);
532 qemu_get_be32s(f
, &s
->ti_rptr
);
533 qemu_get_be32s(f
, &s
->ti_wptr
);
534 qemu_get_buffer(f
, s
->ti_buf
, TI_BUFSZ
);
535 qemu_get_be32s(f
, &s
->sense
);
536 qemu_get_be32s(f
, &s
->dma
);
537 qemu_get_buffer(f
, s
->cmdbuf
, TI_BUFSZ
);
538 qemu_get_be32s(f
, &s
->cmdlen
);
539 qemu_get_be32s(f
, &s
->do_cmd
);
540 qemu_get_be32s(f
, &s
->dma_left
);
545 void esp_scsi_attach(void *opaque
, BlockDriverState
*bd
, int id
)
547 ESPState
*s
= (ESPState
*)opaque
;
550 for (id
= 0; id
< ESP_MAX_DEVS
; id
++) {
551 if (s
->scsi_dev
[id
] == NULL
)
555 if (id
>= ESP_MAX_DEVS
) {
556 DPRINTF("Bad Device ID %d\n", id
);
559 if (s
->scsi_dev
[id
]) {
560 DPRINTF("Destroying device %d\n", id
);
561 scsi_disk_destroy(s
->scsi_dev
[id
]);
563 DPRINTF("Attaching block device %d\n", id
);
564 /* Command queueing is not implemented. */
565 s
->scsi_dev
[id
] = scsi_disk_init(bd
, 0, esp_command_complete
, s
);
568 void *esp_init(BlockDriverState
**bd
, target_phys_addr_t espaddr
,
569 void *dma_opaque
, qemu_irq irq
)
574 s
= qemu_mallocz(sizeof(ESPState
));
580 s
->dma_opaque
= dma_opaque
;
581 sparc32_dma_set_reset_data(dma_opaque
, esp_reset
, s
);
583 esp_io_memory
= cpu_register_io_memory(0, esp_mem_read
, esp_mem_write
, s
);
584 cpu_register_physical_memory(espaddr
, ESP_SIZE
, esp_io_memory
);
588 register_savevm("esp", espaddr
, 3, esp_save
, esp_load
, s
);
589 qemu_register_reset(esp_reset
, s
);