| commit | ca27c052d992da83ce0786d81f85b87cd1f5d301 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 22 Feb 2011 18:19:43 +0000 (22 18:19 +0000) | ||
| committer | Aurelien Jarno <aurelien@aurel32.net> | |
| Mon, 7 Mar 2011 08:46:19 +0000 (7 09:46 +0100) | ||
| tree | 4ea796f79b4bfc9b090eb6c15ed85763203fb2e2 | treesnapshot (tar.gz zip) |
| parent | 3849902cd852d7de0783abc41cb0c57949d567fd | commitdiff |
target-arm: Implement a minimal set of cp14 debug registers
Newer ARM kernels try to probe for whether the CPU has hardware breakpoint
support. For this to work QEMU has to implement a minimal set of the cp14
debug registers. The architecture requires v7 cores to implement debug
and so there is no defined way to report its absence; however in practice
returning a zero DBGDIDR (ie with a reserved value for "debug architecture
version") should cause well-written hw debug users to do the right thing.
We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped
debug components.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Newer ARM kernels try to probe for whether the CPU has hardware breakpoint
support. For this to work QEMU has to implement a minimal set of the cp14
debug registers. The architecture requires v7 cores to implement debug
and so there is no defined way to report its absence; however in practice
returning a zero DBGDIDR (ie with a reserved value for "debug architecture
version") should cause well-written hw debug users to do the right thing.
We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped
debug components.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| target-arm/translate.c | diffblobblamehistory |