| commit | 4d2c2b77f3d0c59642dd2ce799a0fb4c2a91aca8 | |
| author | Blue Swirl <blauwirbel@gmail.com> | |
| Sat, 18 Jun 2011 20:27:05 +0000 (18 20:27 +0000) | ||
| committer | Blue Swirl <blauwirbel@gmail.com> | |
| Sun, 26 Jun 2011 18:25:09 +0000 (26 18:25 +0000) | ||
| tree | 5d4c3ab00b8f2beb54cabf241f4d5e3d0bd82049 | treesnapshot (tar.gz zip) |
| parent | af2be2077734e0ebfc8afbe6caf0f89a1474eef2 | commitdiff |
Sparc32: dummy implementation of MXCC MMU breakpoint registers
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save
and load all MXCC registers.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save
and load all MXCC registers.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
| target-sparc/cpu.h | diffblobblamehistory | |
| target-sparc/machine.c | diffblobblamehistory | |
| target-sparc/op_helper.c | diffblobblamehistory |