target-arm: Remove redundant setting of IT bits before Thumb SWI
commit5de3a9d3b72a9aebc126caee95fe515a900130bf
authorPeter Maydell <peter.maydell@linaro.org>
Fri, 14 Jan 2011 19:39:19 +0000 (14 20:39 +0100)
committerAurelien Jarno <aurelien@aurel32.net>
Fri, 14 Jan 2011 19:39:19 +0000 (14 20:39 +0100)
treef5e5eb21093e5438eb79b2b3146f8c40d1f87824
parent61f74d6a290d606504e4fbd6a94cbee3ce277533
target-arm: Remove redundant setting of IT bits before Thumb SWI

Remove a redundant call to gen_set_condexec() in the translation of Thumb
mode SWI. (SWI and WFI generate "exceptions" which happen after the
execution of the instruction, ie when PC and IT bits have updated.
So the condexec bits at this point are not correct. However, the code
that handles finishing the translation of the TB will write the correct
value of the condexec bits later, so the only effect was that a conditional
Thumb SWI would generate slightly worse code than necessary.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm/translate.c