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2020-08-25	Alistair Francis	target/riscv: Support the Virtual Instruction fault Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Return the exception from invalid CSR... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Support the v0.6 Hypervisor extension... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Only support little endian guests Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Only support a single VSXL length Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Update the CSRs to the v0.6 Hyp extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Update the Hypervisor trap return/entry Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Fix the interrupt cause code Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Convert MSTATUS MTL to GVA Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Don't allow guest to write to htinst Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Do two-stage lookups on hlv/hlvx/hsv... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Allow generating hlv/hlvx/hsv instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-25	Alistair Francis	target/riscv: Allow setting a two-stage lookup in the... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-22	Alistair Francis	hw/intc: ibex_plic: Honour source priorities Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-22	Alistair Francis	hw/intc: ibex_plic: Don't allow repeat interrupts on... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-22	Alistair Francis	hw/intc: ibex_plic: Update the pending irqs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-08-21	Alistair Francis	hw/sd/pl181: Replace fprintf(stderr, "*\n") with error_report() Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>	commit \| commitdiff \| tree
2020-07-14	Alistair Francis	hw/char: Convert the Ibex UART to use the registerfields API Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-07-14	Alistair Francis	hw/char: Convert the Ibex UART to use the qdev Clock... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-07-02	Alistair Francis	hw/riscv: Allow 64 bit access to SiFive CLINT Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	target/riscv: Use a smaller guess size for no-MMU PMP Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	riscv/opentitan: Connect the PLIC device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	hw/intc: Initial commit of lowRISC Ibex PLIC Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	hw/char: Initial commit of Ibex UART Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	riscv/opentitan: Fix the ROM size Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	target/riscv: Implement checks for hfence Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	target/riscv: Move the hfence instructions to the rvh... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	target/riscv: Report errors validating 2nd-stage PTEs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	target/riscv: Set access as data_load when validating... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-19	Alistair Francis	sifive_e: Support the revB machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	riscv: Initial commit of OpenTitan machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Add the lowRISC Ibex CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Don't set PMP feature in the cpu init Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Disable the MMU correctly Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Don't overwrite the reset vector Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	riscv/boot: Add a missing header include Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	riscv: sifive_e: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	docs: deprecated: Update the -bios documentation Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Drop support for ISA spec version 1.09.1 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	target/riscv: Remove the deprecated CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-06-03	Alistair Francis	hw/riscv: spike: Remove deprecated ISA specific machines Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-04-29	Alistair Francis	riscv: AND stage-1 and stage-2 protection flags Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-04-29	Alistair Francis	riscv: Don't use stage-2 PTE lookup protection flags Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-04-29	Alistair Francis	riscv/sifive_u: Add a serial property to the sifive_u SoC Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-04-29	Alistair Francis	riscv/sifive_u: Fix up file ordering Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-30	Alistair Francis	linux-user: Support futex_time64 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-20	Alistair Francis	linux-user/riscv: Update the syscall_nr's to the 5... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-20	Alistair Francis	linux-user/syscall: Add support for clock_gettime64... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-20	Alistair Francis	linux-user: Protect more syscalls Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-03-17	Alistair Francis	target/riscv: Correctly implement TSR trap Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Allow enabling the Hypervisor extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the MSTATUS_MPV_ISSET helper macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add support for the 32-bit MSTATUSH CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Set htval and mtval2 on execptions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Raise the new execptions when 2nd stage... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Implement second stage MMU Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Allow specifying MMU stage Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Respect MPRV and SPRV for floating point ops Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Mark both sstatus and msstatus_hs as... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Disable guest FP support based on virtual... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Only set TB flags with FP status if enabled Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Remove the hret instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add hfence instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add Hypervisor trap return support Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add hypvervisor trap support Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Generate illegal instruction on WFI when V=1 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/ricsv: Flush the TLB on virtulisation mode changes Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add support for virtual interrupt setting Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Extend the SIP CSR to support virtulisation Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Extend the MIE CSR to support virtulisation Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Set VS bits in mideleg for Hyp extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add virtual register swapping function Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add Hypervisor machine CSRs accesses Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add Hypervisor virtual CSRs accesses Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add Hypervisor CSR access functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Dump Hypervisor registers if enabled Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Print priv and virt in disas log Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Fix CSR perm checking for HS mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the force HS exception mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the virtulisation mode Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Rename the H irqs to VS irqs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add support for the new execption numbers Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the Hypervisor CSRs to CPUState Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Add the Hypervisor extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-02-27	Alistair Francis	target/riscv: Convert MIP CSR to target_ulong Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2020-01-17	Alistair Francis	hw/arm: Add the Netduino Plus 2 Signed-off-by: Alistair Francis <alistair@alistair23.me>	commit \| commitdiff \| tree
2020-01-17	Alistair Francis	hw/arm: Add the STM32F4xx SoC Signed-off-by: Alistair Francis <alistair@alistair23.me>	commit \| commitdiff \| tree
2020-01-17	Alistair Francis	hw/misc: Add the STM32F4xx EXTI device Signed-off-by: Alistair Francis <alistair@alistair23.me>	commit \| commitdiff \| tree
2020-01-17	Alistair Francis	hw/misc: Add the STM32F4xx Sysconfig device Signed-off-by: Alistair Francis <alistair@alistair23.me>	commit \| commitdiff \| tree
2019-11-14	Alistair Francis	riscv/virt: Increase flash size Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-11-14	Alistair Francis	opensbi: Upgrade from v0.4 to v0.5 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-11-14	Alistair Francis	target/riscv: Remove atomic accesses to MIP CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/boot: Fix possible memory leak Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/virt: Jump to pflash if specified Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/virt: Add the PFlash CFI01 device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/virt: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add the start-in-flash property Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add QSPI memory region Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
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