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hw/intc: Rename sifive_clint sources to riscv_aclint sources
2021-09-20
A
n
up
Patel
hw
/
intc: Ren
a
me si
f
ive_clint sources to
riscv_aclint
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-12-18
Anu
p
Patel
hw/riscv: sif
i
ve_u: Add
U
ART1 DT
n
ode in t
h
e
gen
e
r
a
ted
D
TB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-11-03
Anup
P
atel
hw/riscv: virt: A
l
l
o
w p
a
ssing custo
m
DTB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-11-03
Anup
Pat
e
l
hw/ri
s
cv: sifive_u: Allow passing
custo
m
DTB
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Patel
hw/risc
v
:
virt: Al
l
ow creating mu
l
tipl
e
N
U
M
A so
c
kets
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Patel
hw/riscv: spike: Allow creati
n
g mu
l
tiple NUMA sockets
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
An
u
p Pat
e
l
hw/riscv: Ad
d
help
e
r
s
for RISC-V multi-
s
ocket NU
M
A
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Pate
l
hw
/
riscv: Allow creati
n
g multiple instance
s
of P
L
IC
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-08-25
Anup Patel
hw/riscv: Allow creating multiple inst
a
nces
o
f
CLINT
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
A
nu
p
Pate
l
h
w
/risc
v
/spi
k
e
: Allow more
t
han one CPUs
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Patel
h
w/riscv/spike: Allow
loadin
g
firmware separately using
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
A
n
up Pa
t
el
hw/ri
s
cv
:
Add optional symbol callback ptr to riscv_load_fir
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-04-29
Anup Pa
t
el
r
is
c
v: Fix Stage2 S
V
32
page table walk
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Anup Patel
hw
/
riscv: Provide r
d
ti
m
e callback for TCG in CLINT
.
.
.
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-27
Anup Pate
l
target/ris
c
v: Emulate TIME CSRs for privilege
d
m
o
de
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anu
p
P
a
tel
MAINTAINERS: Add maintai
n
er entry for
G
oldfish RT
C
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup P
a
tel
riscv: virt: Use
G
oldfish RT
C
device
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Patel
hw: rtc: Add
G
oldfish
RTC de
v
ice
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2020-02-10
Anup Patel
ri
s
cv/virt: Ad
d
syscon reboot an
d
pow
e
ro
f
f
D
T node
s
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
Anup
P
ate
l
tar
g
e
t/riscv/pmp
.
c
:
Fix pmp_decode_na
p
ot()
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
Anup P
a
t
el
sifive_u: Set 'clock-frequen
c
y' DT pro
p
erty for SiFive
.
.
.
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
2018-12-20
Anup Patel
sifive_u:
A
dd clock DT node for GEM
e
thernet
Signed-off-by:
Anup Patel
<anup@brainfault.org>
Signed-off-by:
Anup Patel
<anup.patel@wdc.com>
commit
|
commitdiff
|
tree
