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target/riscv: add zihpm extension flag for TCG
2023-11-07
R
ajnesh K
a
nwal
target/ris
c
v: Add HS-mode virtual in
t
err
u
pt and IRQ
.
.
.
Signed-off-by:
Rajnesh Kanwal
<rkanwal@rivosinc.com>
commit
|
commitdiff
|
tree
2023-11-07
Rajne
s
h Kanwal
t
arget/riscv
:
Add M-mode virt
u
al interrupt and IRQ
.
.
.
Signed-off-by:
Rajnesh Kanwal
<rkanwal@rivosinc.com>
commit
|
commitdiff
|
tree
2023-11-07
R
a
jnesh Kanwal
ta
r
get/riscv: S
p
l
i
t
interrup
t
l
o
gic from riscv_cpu_update_mip
.
Signed-off-by:
Rajnesh Kanwal
<rkanwal@rivosinc.com>
commit
|
commitdiff
|
tree
2023-11-07
R
ajnesh Kan
w
al
target/riscv:
S
e
t VS*
bits
t
o
on
e
i
n mideleg when H
.
.
.
Signed-off-by:
Rajnesh Kanwal
<rkanwal@rivosinc.com>
commit
|
commitdiff
|
tree
2023-11-07
Rajnesh Kanw
a
l
target/
r
i
scv:
Check f
o
r async flag in
c
ase of R
I
SCV_EXCP_SE
M
.
.
.
Signed-off-by:
Rajnesh Kanwal
<rkanwal@rivosinc.com>
commit
|
commitdiff
|
tree
2023-11-07
Rajnesh Kanwal
target/riscv: W
i
t
hout H-mode mask all H
S
mode
i
n
t
urrupts
.
.
.
Signed-off-by:
Rajnesh Kanwal
<rkanwal@rivosinc.com>
commit
|
commitdiff
|
tree
2020-03-17
Rajnesh
K
anwal
target/riscv:
F
i
x VS mode interrupts for
w
arding
.
Signed-off-by:
Rajnesh Kanwal
<rajnesh.kanwal49@gmail.com>
commit
|
commitdiff
|
tree