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target/riscv: add zihpm extension flag for TCG
2023-11-07 Daniel Henrique... target/riscv: add zihpm extension flag for TCG
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv/kvm: add zicntr reg
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv: add zicntr extension flag for TCG
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Mayuresh Chitaletarget/riscv: pmp: Ignore writes when RW=01
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Mayuresh Chitaletarget/riscv: pmp: Clear pmp/smepmp bits on reset
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Himanshu ChauhanAdd epmp to extensions list and rename it to smepmp
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv/riscv-qmp-cmds.c: check CPU accel in query...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv: add riscv_cpu_accelerator_compatible()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv: handle custom props in qmp_query_cpu_model_exp...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv/tcg: add tcg_cpu_finalize_features()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... qapi,risc-v: add query-cpu-model-expansion
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv/kvm/kvm-cpu.c: add missing property getters()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... docs/system/riscv: update 'virt' machine core limit
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... linux-user/riscv: change default cpu to 'max'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Rajnesh Kanwaltarget/riscv: Add HS-mode virtual interrupt and IRQ...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Rajnesh Kanwaltarget/riscv: Add M-mode virtual interrupt and IRQ...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Rajnesh Kanwaltarget/riscv: Split interrupt logic from riscv_cpu_update_mip.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Rajnesh Kanwaltarget/riscv: Set VS* bits to one in mideleg when H...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Rajnesh Kanwaltarget/riscv: Check for async flag in case of RISCV_EXCP_SEM...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Rajnesh Kanwaltarget/riscv: Without H-mode mask all HS mode inturrupts...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv: rename ext_icboz to ext_zicboz
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv: rename ext_icbom to ext_zicbom
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv: rename ext_icsr to ext_zicsr
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-11-07 Daniel Henrique... target/riscv: rename ext_ifencei to ext_zifencei
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2023-10-12 Max Choutarget/riscv: Fix vfwmaccbf16.vf
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: deprecate capital 'Z' CPU properties
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Richard W.M. Jonestarget/riscv: Use env_archcpu for better performance
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/tcg: remove RVG warning
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/kvm: support KVM_GET_REG_LIST
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/kvm: improve 'init_multiext_cfg' error msg
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Clément Chigotgdbstub: replace exit calls with proper shutdown for...
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Clément Chigothw/char: riscv_htif: replace exit calls with proper...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Clément Chigothw/misc/sifive_test.c: replace exit calls with proper...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Clément Chigotsoftmmu: pass the main loop status to gdb "Wxx" packet
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Clément Chigotsoftmmu: add means to pass an exit code when requesting...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/tcg-cpu.c: add extension properties for...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: add riscv_cpu_get_name()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu: move priv spec functions to tcg-cpu.c
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: export isa_edata_arr[]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/tcg: move riscv_cpu_add_misa_properties...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: make misa_ext_cfgs[] 'const'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/tcg: introduce tcg_cpu_instance_init()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: export set_misa()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/kvm: do not use riscv_cpu_add_misa_properties()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: move KVM only files to kvm subdir
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: introduce KVM AccelCPUClass
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: remove kvm-stub.c
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: make riscv_add_satp_mode_properties(...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: move riscv_cpu_add_kvm_properties() to...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: mark extensions arrays as 'const'
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: move 'host' CPU declaration to kvm.c
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: add .instance_post_init()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: move riscv_tcg_ops to tcg-cpu.c
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: move riscv_cpu_validate_set_extensions...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: move riscv_cpu_realize_tcg() to TCG:...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: introduce TCG AccelCPUClass
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Alvin Changdisas/riscv: Fix the typo of inverted order of pmpaddr13...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 liguang.zhangtarget/riscv: Clear CSR values at reset and sync MPSTATE...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: consider user option with RVG
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_up...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: use isa_ext_update_enabled() in init_max_cpu_e...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: make CPUCFG() macro public
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: use offset in isa_ext_is_enabled...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: deprecate the 'any' CPU type
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... avocado, risc-v: add tuxboot tests for 'max' CPU
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: add 'max' CPU type
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: limit cfg->vext_spec log message
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: split vendor exts from riscv_cpu_extensi...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: split non-ratified exts from riscv_cpu_e...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_opt...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: split kvm prop handling to its...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: skip 'bool' check when filtering...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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2023-10-12 Daniel Henrique... target/riscv/cpu.c: split CPU options from riscv_cpu_extensi...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Nikita Shubintarget/riscv: don't read CSR in riscv_csrrw_do64
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Tommy Wutarget/riscv: Align the AIA model to v1.0 ratified...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Leon Schuermanntarget/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX...
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Akihiko Odakitarget/riscv: Allocate itrigger timers only once
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Ard Biesheuveltarget/riscv: Use accelerated helper for AES64KS1I
Cc: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Robbin Ehnlinux-user/riscv: Add new extensions to hwprobe
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Daniel Henrique... hw/intc/riscv_aplic.c fix non-KVM --enable-debug build
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Daniel Henrique... hw/riscv/virt.c: fix non-KVM --enable-debug build
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Vineet Guptariscv: zicond: make non-experimental
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Daniel Henrique... target/riscv: fix satp_mode_finalize() when satp_mode...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Weiwei Litarget/riscv: Update CSR bits name for svadu extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Conor Dooleyhw/riscv: virt: Fix riscv,pmu DT node path
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Yong-Xuan Wangtarget/riscv: select KVM AIA in riscv virt machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Yong-Xuan Wangtarget/riscv: update APLIC and IMSIC to support KVM AIA
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Yong-Xuan Wangtarget/riscv: Create an KVM AIA irqchip
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Yong-Xuan Wangtarget/riscv: check the in-kernel irqchip support
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Yong-Xuan Wangtarget/riscv: support the AIA device emulation with...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 LIU Zhiweilinux-user/riscv: Use abi type for target_ucontext
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Jason Chienhw/intc: Make rtc variable names consistent
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Jason Chienhw/intc: Fix upper/lower mtime write calculation
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 LIU Zhiweitarget/riscv: Fix zfa fleq.d and fltq.d
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2023-09-11 Jason Chientarget/riscv: Add Zihintntl extension ISA string to DTS
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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