From d4452c692488228e6dce193f4f98ac762588d96a Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Thu, 6 Jan 2022 07:39:37 +1000 Subject: [PATCH] hw/riscv: virt: Allow support for 32 cores MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so let's set that as the maximum for the virt board. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435 Signed-off-by: Alistair Francis Reviewed-by: Anup Patel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Message-Id: <20220105213937.1113508-9-alistair.francis@opensource.wdc.com> --- include/hw/riscv/virt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index b8ef99f348..6e9f61ccd9 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,7 +24,7 @@ #include "hw/block/flash.h" #include "qom/object.h" -#define VIRT_CPUS_MAX 8 +#define VIRT_CPUS_MAX 32 #define VIRT_SOCKETS_MAX 8 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") -- 2.11.4.GIT