From 24db877ab6e6dc999016f1f29e59c7eb1539f5d3 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Mon, 28 Sep 2020 12:42:49 +0200 Subject: [PATCH] microvm: add pcie support Uses the existing gpex device which is also used as pcie host bridge on arm/aarch64. For now only a 32bit mmio window and no ioport support. It is disabled by default, use "-machine microvm,pcie=on" to enable. ACPI support must be enabled too because the bus is declared in the DSDT table. Signed-off-by: Gerd Hoffmann Reviewed-by: Michael S. Tsirkin Message-id: 20200928104256.9241-6-kraxel@redhat.com --- hw/i386/Kconfig | 1 + hw/i386/acpi-microvm.c | 12 +++++++ hw/i386/microvm.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++ include/hw/i386/microvm.h | 18 +++++++--- 4 files changed, 111 insertions(+), 4 deletions(-) diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index d0bd8b537d..32aa15533b 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -104,6 +104,7 @@ config MICROVM select MC146818RTC select VIRTIO_MMIO select ACPI_HW_REDUCED + select PCI_EXPRESS_GENERIC_BRIDGE config X86_IOMMU bool diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c index df39c5d3bd..f16f231195 100644 --- a/hw/i386/acpi-microvm.c +++ b/hw/i386/acpi-microvm.c @@ -33,6 +33,8 @@ #include "hw/boards.h" #include "hw/i386/fw_cfg.h" #include "hw/i386/microvm.h" +#include "hw/pci/pci.h" +#include "hw/pci/pcie_host.h" #include "hw/virtio/virtio-mmio.h" #include "acpi-common.h" @@ -87,6 +89,15 @@ static void acpi_dsdt_add_virtio(Aml *scope, } } +static void acpi_dsdt_add_pci(Aml *scope, MicrovmMachineState *mms) +{ + if (mms->pcie != ON_OFF_AUTO_ON) { + return; + } + + acpi_dsdt_add_gpex(scope, &mms->gpex); +} + static void build_dsdt_microvm(GArray *table_data, BIOSLinker *linker, MicrovmMachineState *mms) @@ -112,6 +123,7 @@ build_dsdt_microvm(GArray *table_data, BIOSLinker *linker, GED_MMIO_IRQ, AML_SYSTEM_MEMORY, GED_MMIO_BASE); acpi_dsdt_add_power_button(sb_scope); acpi_dsdt_add_virtio(sb_scope, mms); + acpi_dsdt_add_pci(sb_scope, mms); aml_append(dsdt, sb_scope); /* ACPI 5.0: Table 7-209 System State Package */ diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 60d3272230..273abe28c9 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -46,6 +46,7 @@ #include "hw/virtio/virtio-mmio.h" #include "hw/acpi/acpi.h" #include "hw/acpi/generic_event_device.h" +#include "hw/pci-host/gpex.h" #include "cpu.h" #include "elf.h" @@ -101,6 +102,55 @@ static void microvm_gsi_handler(void *opaque, int n, int level) qemu_set_irq(s->ioapic_irq[n], level); } +static void create_gpex(MicrovmMachineState *mms) +{ + X86MachineState *x86ms = X86_MACHINE(mms); + MemoryRegion *mmio32_alias; + MemoryRegion *mmio64_alias; + MemoryRegion *mmio_reg; + MemoryRegion *ecam_alias; + MemoryRegion *ecam_reg; + DeviceState *dev; + int i; + + dev = qdev_new(TYPE_GPEX_HOST); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + /* Map only the first size_ecam bytes of ECAM space */ + ecam_alias = g_new0(MemoryRegion, 1); + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", + ecam_reg, 0, mms->gpex.ecam.size); + memory_region_add_subregion(get_system_memory(), + mms->gpex.ecam.base, ecam_alias); + + /* Map the MMIO window into system address space so as to expose + * the section of PCI MMIO space which starts at the same base address + * (ie 1:1 mapping for that part of PCI MMIO space visible through + * the window). + */ + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + if (mms->gpex.mmio32.size) { + mmio32_alias = g_new0(MemoryRegion, 1); + memory_region_init_alias(mmio32_alias, OBJECT(dev), "pcie-mmio32", mmio_reg, + mms->gpex.mmio32.base, mms->gpex.mmio32.size); + memory_region_add_subregion(get_system_memory(), + mms->gpex.mmio32.base, mmio32_alias); + } + if (mms->gpex.mmio64.size) { + mmio64_alias = g_new0(MemoryRegion, 1); + memory_region_init_alias(mmio64_alias, OBJECT(dev), "pcie-mmio64", mmio_reg, + mms->gpex.mmio64.base, mms->gpex.mmio64.size); + memory_region_add_subregion(get_system_memory(), + mms->gpex.mmio64.base, mmio64_alias); + } + + for (i = 0; i < GPEX_NUM_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + x86ms->gsi[mms->gpex.irq + i]); + } +} + static void microvm_devices_init(MicrovmMachineState *mms) { X86MachineState *x86ms = X86_MACHINE(mms); @@ -147,6 +197,15 @@ static void microvm_devices_init(MicrovmMachineState *mms) x86ms->acpi_dev = HOTPLUG_HANDLER(dev); } + if (x86_machine_is_acpi_enabled(x86ms) && mms->pcie == ON_OFF_AUTO_ON) { + mms->gpex.mmio32.base = PCIE_MMIO_BASE; + mms->gpex.mmio32.size = PCIE_MMIO_SIZE; + mms->gpex.ecam.base = PCIE_ECAM_BASE; + mms->gpex.ecam.size = PCIE_ECAM_SIZE; + mms->gpex.irq = PCIE_IRQ_BASE; + create_gpex(mms); + } + if (mms->pic == ON_OFF_AUTO_ON || mms->pic == ON_OFF_AUTO_AUTO) { qemu_irq *i8259; @@ -446,6 +505,23 @@ static void microvm_machine_set_rtc(Object *obj, Visitor *v, const char *name, visit_type_OnOffAuto(v, name, &mms->rtc, errp); } +static void microvm_machine_get_pcie(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + OnOffAuto pcie = mms->pcie; + + visit_type_OnOffAuto(v, name, &pcie, errp); +} + +static void microvm_machine_set_pcie(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MicrovmMachineState *mms = MICROVM_MACHINE(obj); + + visit_type_OnOffAuto(v, name, &mms->pcie, errp); +} + static bool microvm_machine_get_isa_serial(Object *obj, Error **errp) { MicrovmMachineState *mms = MICROVM_MACHINE(obj); @@ -521,6 +597,7 @@ static void microvm_machine_initfn(Object *obj) mms->pic = ON_OFF_AUTO_AUTO; mms->pit = ON_OFF_AUTO_AUTO; mms->rtc = ON_OFF_AUTO_AUTO; + mms->pcie = ON_OFF_AUTO_AUTO; mms->isa_serial = true; mms->option_roms = true; mms->auto_kernel_cmdline = true; @@ -587,6 +664,13 @@ static void microvm_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, MICROVM_MACHINE_RTC, "Enable MC146818 RTC"); + object_class_property_add(oc, MICROVM_MACHINE_PCIE, "OnOffAuto", + microvm_machine_get_pcie, + microvm_machine_set_pcie, + NULL, NULL); + object_class_property_set_description(oc, MICROVM_MACHINE_PCIE, + "Enable PCIe"); + object_class_property_add_bool(oc, MICROVM_MACHINE_ISA_SERIAL, microvm_machine_get_isa_serial, microvm_machine_set_isa_serial); diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h index 0d61697c97..91b064575d 100644 --- a/include/hw/i386/microvm.h +++ b/include/hw/i386/microvm.h @@ -25,6 +25,7 @@ #include "hw/boards.h" #include "hw/i386/x86.h" #include "hw/acpi/acpi_dev_interface.h" +#include "hw/pci-host/gpex.h" #include "qom/object.h" /* @@ -42,10 +43,10 @@ * 9 | acpi | acpi (ged) * 10 | pci lnk | * 11 | pci lnk | - * 12 | ps2 | - * 13 | fpu | - * 14 | ide 0 | - * 15 | ide 1 | + * 12 | ps2 | pcie + * 13 | fpu | pcie + * 14 | ide 0 | pcie + * 15 | ide 1 | pcie * 16-23 | pci gsi | virtio */ @@ -59,10 +60,17 @@ #define GED_MMIO_BASE_REGS (GED_MMIO_BASE + 0x200) #define GED_MMIO_IRQ 9 +#define PCIE_MMIO_BASE 0xc0000000 +#define PCIE_MMIO_SIZE 0x20000000 +#define PCIE_ECAM_BASE 0xe0000000 +#define PCIE_ECAM_SIZE 0x10000000 +#define PCIE_IRQ_BASE 12 + /* Machine type options */ #define MICROVM_MACHINE_PIT "pit" #define MICROVM_MACHINE_PIC "pic" #define MICROVM_MACHINE_RTC "rtc" +#define MICROVM_MACHINE_PCIE "pcie" #define MICROVM_MACHINE_ISA_SERIAL "isa-serial" #define MICROVM_MACHINE_OPTION_ROMS "x-option-roms" #define MICROVM_MACHINE_AUTO_KERNEL_CMDLINE "auto-kernel-cmdline" @@ -80,6 +88,7 @@ struct MicrovmMachineState { OnOffAuto pic; OnOffAuto pit; OnOffAuto rtc; + OnOffAuto pcie; bool isa_serial; bool option_roms; bool auto_kernel_cmdline; @@ -89,6 +98,7 @@ struct MicrovmMachineState { bool kernel_cmdline_fixed; Notifier machine_done; Notifier powerdown_req; + struct GPEXConfig gpex; }; #define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm") -- 2.11.4.GIT