From 17fded9d963c767781485fdbffd6be005f7eea5a Mon Sep 17 00:00:00 2001 From: Luis Pires Date: Fri, 29 Oct 2021 16:24:10 -0300 Subject: [PATCH] target/ppc: Do not update nip on DFP instructions Before moving the existing DFP instructions to decodetree, drop the nip update that shouldn't be done for these instructions. Signed-off-by: Luis Pires Reviewed-by: Richard Henderson Message-Id: <20211029192417.400707-9-luis.pires@eldorado.org.br> Signed-off-by: David Gibson --- target/ppc/translate/dfp-impl.c.inc | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc index e149777481..1431d955c6 100644 --- a/target/ppc/translate/dfp-impl.c.inc +++ b/target/ppc/translate/dfp-impl.c.inc @@ -15,7 +15,6 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ rd = gen_fprp_ptr(rD(ctx->opcode)); \ ra = gen_fprp_ptr(rA(ctx->opcode)); \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ @@ -36,7 +35,6 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ ra = gen_fprp_ptr(rA(ctx->opcode)); \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ @@ -54,7 +52,6 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ uim = tcg_const_i32(UIMM5(ctx->opcode)); \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ @@ -72,7 +69,6 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ ra = gen_fprp_ptr(rA(ctx->opcode)); \ dcm = tcg_const_i32(DCM(ctx->opcode)); \ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ @@ -90,7 +86,6 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ rt = gen_fprp_ptr(rD(ctx->opcode)); \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \ @@ -114,7 +109,6 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ rt = gen_fprp_ptr(rD(ctx->opcode)); \ ra = gen_fprp_ptr(rA(ctx->opcode)); \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ @@ -137,7 +131,6 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ rt = gen_fprp_ptr(rD(ctx->opcode)); \ rb = gen_fprp_ptr(rB(ctx->opcode)); \ gen_helper_##name(cpu_env, rt, rb); \ @@ -157,7 +150,6 @@ static void gen_##name(DisasContext *ctx) \ gen_exception(ctx, POWERPC_EXCP_FPU); \ return; \ } \ - gen_update_nip(ctx, ctx->base.pc_next - 4); \ rt = gen_fprp_ptr(rD(ctx->opcode)); \ rs = gen_fprp_ptr(fprfld(ctx->opcode)); \ i32 = tcg_const_i32(i32fld(ctx->opcode)); \ -- 2.11.4.GIT