| commit | f7697f0e629eb75d411bc6f314c6fff68fa4c238 | |
| author | Yifei Jiang <jiangyifei@huawei.com> | |
| Mon, 26 Oct 2020 11:55:26 +0000 (26 19:55 +0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 3 Nov 2020 15:17:23 +0000 (3 07:17 -0800) | ||
| tree | 51da5a47ea36ea88aa2b44799b6ab2eab912a0a0 | treesnapshot (tar.gz zip) |
| parent | 284d697c74ef3f4210cbccc5cd6b4894740e4ab3 | commitdiff |
target/riscv: Add basic vmstate description of CPU
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/internals.h | diffblobblamehistory | |
| target/riscv/machine.c | [new file with mode: 0644] | blob |
| target/riscv/meson.build | diffblobblamehistory |