| commit | f5e328fef057a79ee40a93cdb27bf0de7991973e | |
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | |
| Fri, 24 May 2024 11:32:55 +0000 (24 13:32 +0200) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 30 May 2024 12:21:06 +0000 (30 13:21 +0100) | ||
| tree | e41221fbab01eadd895f1f25d2c2c74eef3d246d | treesnapshot (tar.gz zip) |
| parent | 3b2fe44bb7f605f179e5e7feb2c13c2eb3abbb80 | commitdiff |
hw/intc/arm_gic: Fix set pending of PPIs
According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending
Registers, GICD_ISPENDRn":
"In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected
processor. This register holds the Set-pending bits for interrupts 0-31."
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Message-id: 20240524113256.8102-2-sebastian.huber@embedded-brains.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending
Registers, GICD_ISPENDRn":
"In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected
processor. This register holds the Set-pending bits for interrupts 0-31."
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Message-id: 20240524113256.8102-2-sebastian.huber@embedded-brains.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/intc/arm_gic.c | diffblobblamehistory |