| commit | f0fc1c29a8163ce383d3bcb3aac0964747d2d8b1 | |
| author | Frederic Barrat <fbarrat@linux.ibm.com> | |
| Thu, 1 Jun 2023 12:13:29 +0000 (1 14:13 +0200) | ||
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | |
| Sat, 10 Jun 2023 13:19:24 +0000 (10 10:19 -0300) | ||
| tree | 26007ae61b348975c0337427d24d9804ec6e762a | treesnapshot (tar.gz zip) |
| parent | 32af01f83a763ccbba39c1cbc424e1b724d233df | commitdiff |
pnv/xive2: Allow writes to the Physical Thread Enable registers
Fix what was probably a silly mistake and allow to write the Physical
Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET
variant so it went unnoticed, but there's no reason to discard a write
to the full register, it is Read-Write.
Fixes: da71b7e3ed45 ("ppc/pnv: Add a XIVE2 controller to the POWER10 chip")
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-4-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Fix what was probably a silly mistake and allow to write the Physical
Thread enable registers 0 and 1. Skiboot prefers to use the ENx_SET
variant so it went unnoticed, but there's no reason to discard a write
to the full register, it is Read-Write.
Fixes: da71b7e3ed45 ("ppc/pnv: Add a XIVE2 controller to the POWER10 chip")
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-4-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| hw/intc/pnv_xive2.c | diffblobblamehistory |