| commit | eb02cc3f89013612cb05df23b5441741e902bbd2 | |
| author | Aurelien Jarno <aurelien@aurel32.net> | |
| Wed, 15 Jul 2015 15:05:09 +0000 (15 17:05 +0200) | ||
| committer | Leon Alrae <leon.alrae@imgtec.com> | |
| Thu, 13 Aug 2015 15:22:52 +0000 (13 16:22 +0100) | ||
| tree | 3c520356c13e7cc307cb77db087d1bc795fb8b5a | treesnapshot (tar.gz zip) |
| parent | aff2bc6dc6d839caf6df0900437cc2cc9e180605 | commitdiff |
target-mips: simplify LWL/LDL mask generation
The LWL/LDL instructions mask the GPR with a mask depending on the
address alignement. It is currently computed by doing:
mask = 0x7fffffffffffffffull >> (t1 ^ 63)
It's simpler to generate it by doing:
mask = ~(-1 << t1)
It uses one TCG instruction less, and it avoids a 32/64-bit constant
loading which can take a few instructions on RISC hosts.
Cc: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
The LWL/LDL instructions mask the GPR with a mask depending on the
address alignement. It is currently computed by doing:
mask = 0x7fffffffffffffffull >> (t1 ^ 63)
It's simpler to generate it by doing:
mask = ~(-1 << t1)
It uses one TCG instruction less, and it avoids a 32/64-bit constant
loading which can take a few instructions on RISC hosts.
Cc: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| target-mips/translate.c | diffblobblamehistory |