| commit | dc5e072188ea622071bab47c4f899817d6ef1295 | |
| author | Nicholas Piggin <npiggin@gmail.com> | |
| Thu, 22 Jun 2023 09:33:55 +0000 (22 19:33 +1000) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Sun, 25 Jun 2023 20:41:30 +0000 (25 22:41 +0200) | ||
| tree | 134ba5eddeae653d47c5057817695d08a1f2c2e3 | treesnapshot (tar.gz zip) |
| parent | 516cd737330a9b4d90a66136ebf738c4653b4e78 | commitdiff |
spapr: TCG allow up to 8-thread SMT on POWER8 and newer CPUs
PPC TCG supports SMT CPU configurations for non-hypervisor state, so
permit POWER8-10 pseries machines to enable SMT.
This requires PIR and TIR be set, because that's how sibling thread
matching is done by TCG.
spapr's nested-HV capability does not currently coexist with SMT, so
that combination is prohibited (interestingly somewhat analogous to
LPAR-per-core mode on real hardware which also does not support KVM).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: Also test smp_threads when checking for POWER8 CPU and above ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
PPC TCG supports SMT CPU configurations for non-hypervisor state, so
permit POWER8-10 pseries machines to enable SMT.
This requires PIR and TIR be set, because that's how sibling thread
matching is done by TCG.
spapr's nested-HV capability does not currently coexist with SMT, so
that combination is prohibited (interestingly somewhat analogous to
LPAR-per-core mode on real hardware which also does not support KVM).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: Also test smp_threads when checking for POWER8 CPU and above ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| hw/ppc/spapr.c | diffblobblamehistory | |
| hw/ppc/spapr_caps.c | diffblobblamehistory | |
| hw/ppc/spapr_cpu_core.c | diffblobblamehistory |