| commit | ce8f0905a59232982c8a220169e11c14c73e7dea | |
| author | Rob Herring <rob.herring@linaro.org> | |
| Tue, 18 Mar 2014 18:18:40 +0000 (18 13:18 -0500) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 18 Mar 2014 19:38:55 +0000 (18 19:38 +0000) | ||
| tree | 821ac781cd68fdd8beca82c136d5ec1e10005f61 | treesnapshot (tar.gz zip) |
| parent | 22709e90a270a36418f1b1d5d3277016eec1edc2 | commitdiff |
pl011: fix UARTRSR accesses corrupting the UARTCR value
Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be
corrupted if the UARTRSR is ever written. Fix by implementing a correct
model of the UARTRSR/UARTECR register. Reads of this register simply
reflect the error bits in data register. Only breaks can be triggered in
QEMU. With the pl011_can_receive function, we effectively have flow
control between the host and the model. Framing and parity errors simply
don't make sense in the model and will never occur.
Signed-off-by: Rob Herring <rob.herring@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1395166721-15716-3-git-send-email-robherring2@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be
corrupted if the UARTRSR is ever written. Fix by implementing a correct
model of the UARTRSR/UARTECR register. Reads of this register simply
reflect the error bits in data register. Only breaks can be triggered in
QEMU. With the pl011_can_receive function, we effectively have flow
control between the host and the model. Framing and parity errors simply
don't make sense in the model and will never occur.
Signed-off-by: Rob Herring <rob.herring@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1395166721-15716-3-git-send-email-robherring2@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/char/pl011.c | diffblobblamehistory |