| commit | c7efab4fc1fe5092136305a2cae67fca03f4f9c5 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Sun, 25 Aug 2019 22:02:54 +0000 (25 15:02 -0700) | ||
| committer | Richard Henderson <richard.henderson@linaro.org> | |
| Wed, 4 Sep 2019 19:48:43 +0000 (4 12:48 -0700) | ||
| tree | 17c8eb391a8d03a3002cee3235df59bce50a7dd5 | treesnapshot (tar.gz zip) |
| parent | b72e3ff65880f2b894a2692e2b0a14424058a919 | commitdiff |
target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
These registers are read-only and implementation specific.
Initiailize VR for the first time; take the OR1200 values
from the verilog source.
Note that moving fields within CPUOpenRISCState does not
affect migration.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
These registers are read-only and implementation specific.
Initiailize VR for the first time; take the OR1200 values
from the verilog source.
Note that moving fields within CPUOpenRISCState does not
affect migration.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| target/openrisc/cpu.c | diffblobblamehistory | |
| target/openrisc/cpu.h | diffblobblamehistory | |
| target/openrisc/sys_helper.c | diffblobblamehistory |