target/riscv: add support for svinval extension
commitc5d77ddd8ebcd33da9561982e29c8f4b2dec0978
authorWeiwei Li <liweiwei@iscas.ac.cn>
Fri, 4 Feb 2022 02:26:57 +0000 (4 10:26 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:25:52 +0000 (16 12:25 +1000)
treeb56b397c7cb881dda2aa118cba93ca6296f5ddfc
parent2bacb22446a45b07f542d32b6d760da757233b20
target/riscv: add support for svinval extension

- sinval.vma, hinval.vvma and hinval.gvma do the same as sfence.vma, hfence.vvma and hfence.gvma except extension check
- do nothing other than extension check for sfence.w.inval and sfence.inval.ir

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_svinval.c.inc [new file with mode: 0644]
target/riscv/translate.c