| commit | a59b1ed618415212c5f0f05abc1192e14ad5fdbb | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 19 Nov 2020 21:56:05 +0000 (19 21:56 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 10 Dec 2020 11:44:55 +0000 (10 11:44 +0000) | ||
| tree | 59dff8ef44f6c10ecd9a2a759751eeca30c09012 | treesnapshot (tar.gz zip) |
| parent | 99c7834fba4e5f204a82a1c456de2148b9595135 | commitdiff |
target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR
are zeroed for an exception taken to Non-secure state; for an
exception taken to Secure state they become UNKNOWN, and we chose to
leave them at their previous values.
In v8.1M the behaviour is specified more tightly and these registers
are always zeroed regardless of the security state that the exception
targets (see rule R_KPZV). Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-17-peter.maydell@linaro.org
In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR
are zeroed for an exception taken to Non-secure state; for an
exception taken to Secure state they become UNKNOWN, and we chose to
leave them at their previous values.
In v8.1M the behaviour is specified more tightly and these registers
are always zeroed regardless of the security state that the exception
targets (see rule R_KPZV). Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-17-peter.maydell@linaro.org
| target/arm/m_helper.c | diffblobblamehistory |