| commit | 984eda58f20763ffb56b7aff34ad60bdeb118eb1 | |
| author | Nicholas Piggin <npiggin@gmail.com> | |
| Wed, 21 Jun 2023 11:09:38 +0000 (21 21:09 +1000) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Sun, 25 Jun 2023 20:41:30 +0000 (25 22:41 +0200) | ||
| tree | 28a1d99a100d81399988af66750411843cea763e | treesnapshot (tar.gz zip) |
| parent | 488aad116651f9838767fd53d5660e6702925c14 | commitdiff |
target/ppc: Fix sc instruction handling of LEV field
The top bits of the LEV field of the sc instruction are to be treated as
as a reserved field rather than a reserved value, meaning LEV is
effectively the bottom bit. LEV=0xF should be treated as LEV=1 and be
a hypercall, for example.
This changes the instruction execution to just set lev from the low bit
of the field. Processors which don't support the LEV field will continue
to ignore it.
ISA v3.1 defines LEV to be 2 bits, in order to add the 'sc 2' ultracall
instruction. TCG does not support Ultravisor, so don't worry about
that bit.
Suggested-by: "Harsh Prateek Bora" <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
The top bits of the LEV field of the sc instruction are to be treated as
as a reserved field rather than a reserved value, meaning LEV is
effectively the bottom bit. LEV=0xF should be treated as LEV=1 and be
a hypercall, for example.
This changes the instruction execution to just set lev from the low bit
of the field. Processors which don't support the LEV field will continue
to ignore it.
ISA v3.1 defines LEV to be 2 bits, in order to add the 'sc 2' ultracall
instruction. TCG does not support Ultravisor, so don't worry about
that bit.
Suggested-by: "Harsh Prateek Bora" <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| target/ppc/translate.c | diffblobblamehistory |