| commit | 7b19a3554d2df22d29c75319a1dac17615d1b20e | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Mon, 22 Apr 2024 17:07:22 +0000 (22 10:07 -0700) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 30 Apr 2024 14:01:07 +0000 (30 15:01 +0100) | ||
| tree | 8e18b57d647f6562d854055d20302a633a7fb8e3 | treesnapshot (tar.gz zip) |
| parent | a8aa8af99f87f20beca58f647a347ba576d59444 | commitdiff |
target/arm: Restrict translation disabled alignment check to VMSA
For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable. This means that it should not
have alignment restrictions enforced.
Cc: qemu-stable@nongnu.org
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
Reported-by: Clément Chigot <chigot@adacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Clément Chigot <chigot@adacore.com>
Message-id: 20240422170722.117409-1-richard.henderson@linaro.org
[PMM: trivial comment, commit message tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
For cpus using PMSA, when the MPU is disabled, the default memory
type is Normal, Non-cachable. This means that it should not
have alignment restrictions enforced.
Cc: qemu-stable@nongnu.org
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
Reported-by: Clément Chigot <chigot@adacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Clément Chigot <chigot@adacore.com>
Message-id: 20240422170722.117409-1-richard.henderson@linaro.org
[PMM: trivial comment, commit message tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/tcg/hflags.c | diffblobblamehistory |