target/ppc: Cache per-pmc insn and cycle count settings
commit6e8b990354d244ad5af40c747fdf3c008962b4e3
authorRichard Henderson <richard.henderson@linaro.org>
Tue, 4 Jan 2022 06:55:34 +0000 (4 07:55 +0100)
committerCédric Le Goater <clg@kaod.org>
Tue, 4 Jan 2022 06:55:34 +0000 (4 07:55 +0100)
tree0e65c2d0e34eadbadf6ec696446caab29ba850be
parent93130c8475692b1e52e3d3c3beedc3a79b4562d5
target/ppc: Cache per-pmc insn and cycle count settings

This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[danielhb: fixed PMC4 cyc_cnt shift, insn run latch code,
           MMCR0_FC handling, "PMC[1-6]" comment]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220103224746.167831-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
target/ppc/cpu.h
target/ppc/cpu_init.c
target/ppc/helper_regs.c
target/ppc/machine.c
target/ppc/power8-pmu.c
target/ppc/power8-pmu.h