| commit | 6cfcf77573fb9714afd09b9b9ead05e002102243 | |
| author | Emmanuel Blot <emmanuel.blot@sifive.com> | |
| Wed, 21 Apr 2021 13:32:36 +0000 (21 15:32 +0200) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Tue, 11 May 2021 10:02:07 +0000 (11 20:02 +1000) | ||
| tree | 922be9bc1136a3737993efec4b0b989353a2958b | treesnapshot (tar.gz zip) |
| parent | 3a7f7757ba95a374f73ed08cd5a9af366299ef81 | commitdiff |
target/riscv: fix a typo with interrupt names
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu.c | diffblobblamehistory |