| commit | 5bddf92e689c0a3da57f4fd17b83d4eb1e436b80 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 4 May 2021 12:09:11 +0000 (4 13:09 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 10 May 2021 16:21:54 +0000 (10 17:21 +0100) | ||
| tree | b7c25948f690e9d2b97298874a22159167e156f0 | treesnapshot (tar.gz zip) |
| parent | c52c266d24b10f1482602e6d22938d9e21f874f5 | commitdiff |
hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping
On some boards, SCC config register CFG0 bit 0 controls whether
parts of the board memory map are remapped. Support this with:
* a device property scc-cfg0 so the board can specify the
initial value of the CFG0 register
* an outbound GPIO line which tracks bit 0 and which the board
can wire up to provide the remapping
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210504120912.23094-3-peter.maydell@linaro.org
On some boards, SCC config register CFG0 bit 0 controls whether
parts of the board memory map are remapped. Support this with:
* a device property scc-cfg0 so the board can specify the
initial value of the CFG0 register
* an outbound GPIO line which tracks bit 0 and which the board
can wire up to provide the remapping
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210504120912.23094-3-peter.maydell@linaro.org
| hw/misc/mps2-scc.c | diffblobblamehistory | |
| include/hw/misc/mps2-scc.h | diffblobblamehistory |