| commit | 58044b5cf5f30eb298709696ddbafdf547c1291c | |
| author | Andrew Jeffery <andrew@aj.id.au> | |
| Mon, 1 Jul 2019 16:26:16 +0000 (1 17:26 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 1 Jul 2019 16:28:59 +0000 (1 17:28 +0100) | ||
| tree | 937fdc58114c448757c26e746c52b947654c4f93 | treesnapshot (tar.gz zip) |
| parent | 8137355e850f634715209087ab664b271996db42 | commitdiff |
aspeed/timer: Status register contains reload for stopped timer
From the datasheet:
This register stores the current status of counter #N. When timer
enable bit TMC30[N * b] is disabled, the reload register will be
loaded into this counter. When timer bit TMC30[N * b] is set, the
counter will start to decrement. CPU can update this register value
when enable bit is set.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-9-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
From the datasheet:
This register stores the current status of counter #N. When timer
enable bit TMC30[N * b] is disabled, the reload register will be
loaded into this counter. When timer bit TMC30[N * b] is set, the
counter will start to decrement. CPU can update this register value
when enable bit is set.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190618165311.27066-9-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/timer/aspeed_timer.c | diffblobblamehistory |