| commit | 4a7d2b7e5cebd00bdcc842517174ad33fd4934cb | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Wed, 17 Aug 2022 15:08:20 +0000 (17 17:08 +0200) | ||
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | |
| Wed, 31 Aug 2022 17:08:06 +0000 (31 14:08 -0300) | ||
| tree | fe953067f4153747da8a2858f9bf2d2ecce1f666 | treesnapshot (tar.gz zip) |
| parent | 629cae617039e03d5bfdc0120ade69135a009d33 | commitdiff |
ppc/ppc405: QOM'ify CPC
The CPC controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <23393cb91a2c6c560a4461b3e9d1baa48ae28f74.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
The CPC controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <23393cb91a2c6c560a4461b3e9d1baa48ae28f74.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| hw/ppc/ppc405.h | diffblobblamehistory | |
| hw/ppc/ppc405_uc.c | diffblobblamehistory |