| commit | 41bf234d8e35e9273290df278e2aeb88c0c50a4f | |
| author | Rabin Vincent <rabin@rab.in> | |
| Sun, 6 Nov 2011 16:01:08 +0000 (6 16:01 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Sun, 6 Nov 2011 16:01:08 +0000 (6 16:01 +0000) | ||
| tree | 5f563eea221ef4b9c0b169bf53b19c084f41e22c | treesnapshot (tar.gz zip) |
| parent | 932eacc158c064935c7bab920c88a93a629e1ca4 | commitdiff |
arm_gic: handle banked enable bits for per-cpu interrupts
The first enable set/clear register (which controls the PPIs and SGIs)
is supposed to be banked for each processor. Currently it is just
handled globally and this prevents recent SMP Linux kernels from
booting, because CPU0 stops receiving localtimer interrupts when CPU1
disables them locally.
To fix this, allow the enable bits to be enabled per-cpu. For SPIs,
always enable/disable ALL_CPU_MASK.
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The first enable set/clear register (which controls the PPIs and SGIs)
is supposed to be banked for each processor. Currently it is just
handled globally and this prevents recent SMP Linux kernels from
booting, because CPU0 stops receiving localtimer interrupts when CPU1
disables them locally.
To fix this, allow the enable bits to be enabled per-cpu. For SPIs,
always enable/disable ALL_CPU_MASK.
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/arm_gic.c | diffblobblamehistory |