| commit | 3144fbc94240f5c7dceaf0973e37bb7d14cd4021 | |
| author | Gavin Shan <gshan@redhat.com> | |
| Tue, 14 Nov 2023 23:56:14 +0000 (15 09:56 +1000) | ||
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | |
| Fri, 5 Jan 2024 15:20:14 +0000 (5 16:20 +0100) | ||
| tree | 8c2e8ed62a46aacf625710ee424fbaced51fbbbc | treesnapshot (tar.gz zip) |
| parent | 72b381f1339e52a9fc672c39b2611dc1a79899ca | commitdiff |
target/riscv: Use generic cpu_list()
Before it's applied:
[gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ?
any
max
rv64
shakti-c
sifive-e51
sifive-u54
thead-c906
veyron-v1
x-rv128
After it's applied:
[gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ?
Available CPUs:
any
max
rv64
shakti-c
sifive-e51
sifive-u54
thead-c906
veyron-v1
x-rv128
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231114235628.534334-18-gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Before it's applied:
[gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ?
any
max
rv64
shakti-c
sifive-e51
sifive-u54
thead-c906
veyron-v1
x-rv128
After it's applied:
[gshan@gshan q]$ ./build/qemu-system-riscv64 -cpu ?
Available CPUs:
any
max
rv64
shakti-c
sifive-e51
sifive-u54
thead-c906
veyron-v1
x-rv128
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231114235628.534334-18-gshan@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/cpu.h | diffblobblamehistory |