| commit | 2357bca5328e9f6b1e0f14a3ac62a7f8b1aef557 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 1 Feb 2019 14:55:43 +0000 (1 14:55 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 1 Feb 2019 14:55:43 +0000 (1 14:55 +0000) | ||
| tree | dbe5f92de22624f50849b84d5b78cdd0043e80b3 | treesnapshot (tar.gz zip) |
| parent | e0b00f1b92d700171cfe39fac39de9fa75c1aecd | commitdiff |
hw/arm/armsse: Add unimplemented-device stub for cache control registers
The SSE-200 gives each CPU a register bank to use to control its
L1 instruction cache. Put in an unimplemented-device stub for this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
The SSE-200 gives each CPU a register bank to use to control its
L1 instruction cache. Put in an unimplemented-device stub for this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190121185118.18550-18-peter.maydell@linaro.org
| hw/arm/armsse.c | diffblobblamehistory | |
| include/hw/arm/armsse.h | diffblobblamehistory |