| commit | 0af3f115e68ea9b46fe56fa7af554c61a966a23c | |
| author | Weiwei Li <liweiwei@iscas.ac.cn> | |
| Fri, 24 Feb 2023 04:08:51 +0000 (24 12:08 +0800) | ||
| committer | Palmer Dabbelt <palmer@rivosinc.com> | |
| Thu, 2 Mar 2023 01:28:17 +0000 (1 17:28 -0800) | ||
| tree | 063c09bb8d85218e197347e7393fdd66a85e85d6 | treesnapshot (tar.gz zip) |
| parent | 7a6613da99ccb0a80adda550722df387736d77da | commitdiff |
target/riscv: Add *envcfg.HADE related check in address translation
When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled
during single-stage address translation. When the hypervisor extension is
implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is
enabled during G-stage address translation.
Set *envcfg.HADE default true for backward compatibility.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-6-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled
during single-stage address translation. When the hypervisor extension is
implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is
enabled during G-stage address translation.
Set *envcfg.HADE default true for backward compatibility.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-6-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| target/riscv/cpu.c | diffblobblamehistory | |
| target/riscv/cpu_helper.c | diffblobblamehistory |