| commit | 04829ce334bece78d4fa1d0fdbc8bc27dae9b242 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 6 Oct 2017 15:46:49 +0000 (6 16:46 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 6 Oct 2017 15:46:49 +0000 (6 16:46 +0100) | ||
| tree | 970a97ab62d9cb35de8308e010ce395ab6783309 | treesnapshot (tar.gz zip) |
| parent | b81ac0eb6315e602b18439961e0538538e4aed4f | commitdiff |
nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit
When we added support for the new SHCSR bits in v8M in commit
437d59c17e9 the code to support writing to the new HARDFAULTPENDED
bit was accidentally only added for non-secure writes; the
secure banked version of the bit should also be writable.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1506092407-26985-21-git-send-email-peter.maydell@linaro.org
When we added support for the new SHCSR bits in v8M in commit
437d59c17e9 the code to support writing to the new HARDFAULTPENDED
bit was accidentally only added for non-secure writes; the
secure banked version of the bit should also be writable.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1506092407-26985-21-git-send-email-peter.maydell@linaro.org
| hw/intc/armv7m_nvic.c | diffblobblamehistory |