hw/i386/microvm-dt.c

   1 /*
   2  * microvm device tree support
   3  *
   4  * This generates an device tree for microvm and exports it via fw_cfg
   5  * as "etc/fdt" to the firmware (edk2 specifically).
   6  *
   7  * The use case is to allow edk2 find the pcie ecam and the virtio
   8  * devices, without adding an ACPI parser, reusing the fdt parser
   9  * which is needed anyway for the arm platform.
  10  *
  11  * Note 1: The device tree is incomplete. CPUs and memory is missing
  12  *         for example, those can be detected using other fw_cfg files.
  13  *         Also pci ecam irq routing is not there, edk2 doesn't use
  14  *         interrupts.
  15  *
  16  * Note 2: This is for firmware only. OSes should use the more
  17  *         complete ACPI tables for hardware discovery.
  18  *
  19  * ----------------------------------------------------------------------
  20  *
  21  * This program is free software; you can redistribute it and/or modify it
  22  * under the terms and conditions of the GNU General Public License,
  23  * version 2 or later, as published by the Free Software Foundation.
  24  *
  25  * This program is distributed in the hope it will be useful, but WITHOUT
  26  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  27  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  28  * more details.
  29  *
  30  * You should have received a copy of the GNU General Public License along with
  31  * this program.  If not, see <http://www.gnu.org/licenses/>.
  32  */
  33 #include "qemu/osdep.h"
  34 #include "qemu/cutils.h"
  35 #include "sysemu/device_tree.h"
  36 #include "hw/char/serial.h"
  37 #include "hw/i386/fw_cfg.h"
  38 #include "hw/rtc/mc146818rtc.h"
  39 #include "hw/sysbus.h"
  40 #include "hw/virtio/virtio-mmio.h"
  41 #include "hw/usb/xhci.h"
  42
  43 #include "microvm-dt.h"
  44
  45 static bool debug;
  46
  47 static void dt_add_microvm_irq(MicrovmMachineState *mms,
  48                                const char *nodename, uint32_t irq)
  49 {
  50     int index = 0;
  51
  52     if (irq >= IO_APIC_SECONDARY_IRQBASE) {
  53         irq -= IO_APIC_SECONDARY_IRQBASE;
  54         index++;
  55     }
  56
  57     qemu_fdt_setprop_cell(mms->fdt, nodename, "interrupt-parent",
  58                           mms->ioapic_phandle[index]);
  59     qemu_fdt_setprop_cells(mms->fdt, nodename, "interrupts", irq, 0);
  60 }
  61
  62 static void dt_add_virtio(MicrovmMachineState *mms, VirtIOMMIOProxy *mmio)
  63 {
  64     SysBusDevice *dev = SYS_BUS_DEVICE(mmio);
  65     VirtioBusState *mmio_virtio_bus = &mmio->bus;
  66     BusState *mmio_bus = &mmio_virtio_bus->parent_obj;
  67     char *nodename;
  68
  69     if (QTAILQ_EMPTY(&mmio_bus->children)) {
  70         return;
  71     }
  72
  73     hwaddr base = dev->mmio[0].addr;
  74     hwaddr size = 512;
  75     unsigned index = (base - VIRTIO_MMIO_BASE) / size;
  76     uint32_t irq = mms->virtio_irq_base + index;
  77
  78     nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
  79     qemu_fdt_add_subnode(mms->fdt, nodename);
  80     qemu_fdt_setprop_string(mms->fdt, nodename, "compatible", "virtio,mmio");
  81     qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
  82     qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0);
  83     dt_add_microvm_irq(mms, nodename, irq);
  84     g_free(nodename);
  85 }
  86
  87 static void dt_add_xhci(MicrovmMachineState *mms)
  88 {
  89     const char compat[] = "generic-xhci";
  90     uint32_t irq = MICROVM_XHCI_IRQ;
  91     hwaddr base = MICROVM_XHCI_BASE;
  92     hwaddr size = XHCI_LEN_REGS;
  93     char *nodename;
  94
  95     nodename = g_strdup_printf("/usb@%" PRIx64, base);
  96     qemu_fdt_add_subnode(mms->fdt, nodename);
  97     qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(compat));
  98     qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
  99     qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0);
 100     dt_add_microvm_irq(mms, nodename, irq);
 101     g_free(nodename);
 102 }
 103
 104 static void dt_add_pcie(MicrovmMachineState *mms)
 105 {
 106     hwaddr base = PCIE_MMIO_BASE;
 107     int nr_pcie_buses;
 108     char *nodename;
 109
 110     nodename = g_strdup_printf("/pcie@%" PRIx64, base);
 111     qemu_fdt_add_subnode(mms->fdt, nodename);
 112     qemu_fdt_setprop_string(mms->fdt, nodename,
 113                             "compatible", "pci-host-ecam-generic");
 114     qemu_fdt_setprop_string(mms->fdt, nodename, "device_type", "pci");
 115     qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 3);
 116     qemu_fdt_setprop_cell(mms->fdt, nodename, "#size-cells", 2);
 117     qemu_fdt_setprop_cell(mms->fdt, nodename, "linux,pci-domain", 0);
 118     qemu_fdt_setprop(mms->fdt, nodename, "dma-coherent", NULL, 0);
 119
 120     qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg",
 121                                  2, PCIE_ECAM_BASE, 2, PCIE_ECAM_SIZE);
 122     if (mms->gpex.mmio64.size) {
 123         qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "ranges",
 124
 125                                      1, FDT_PCI_RANGE_MMIO,
 126                                      2, mms->gpex.mmio32.base,
 127                                      2, mms->gpex.mmio32.base,
 128                                      2, mms->gpex.mmio32.size,
 129
 130                                      1, FDT_PCI_RANGE_MMIO_64BIT,
 131                                      2, mms->gpex.mmio64.base,
 132                                      2, mms->gpex.mmio64.base,
 133                                      2, mms->gpex.mmio64.size);
 134     } else {
 135         qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "ranges",
 136
 137                                      1, FDT_PCI_RANGE_MMIO,
 138                                      2, mms->gpex.mmio32.base,
 139                                      2, mms->gpex.mmio32.base,
 140                                      2, mms->gpex.mmio32.size);
 141     }
 142
 143     nr_pcie_buses = PCIE_ECAM_SIZE / PCIE_MMCFG_SIZE_MIN;
 144     qemu_fdt_setprop_cells(mms->fdt, nodename, "bus-range", 0,
 145                            nr_pcie_buses - 1);
 146 }
 147
 148 static void dt_add_ioapic(MicrovmMachineState *mms, SysBusDevice *dev)
 149 {
 150     hwaddr base = dev->mmio[0].addr;
 151     char *nodename;
 152     uint32_t ph;
 153     int index;
 154
 155     switch (base) {
 156     case IO_APIC_DEFAULT_ADDRESS:
 157         index = 0;
 158         break;
 159     case IO_APIC_SECONDARY_ADDRESS:
 160         index = 1;
 161         break;
 162     default:
 163         fprintf(stderr, "unknown ioapic @ %" PRIx64 "\n", base);
 164         return;
 165     }
 166
 167     nodename = g_strdup_printf("/ioapic%d@%" PRIx64, index + 1, base);
 168     qemu_fdt_add_subnode(mms->fdt, nodename);
 169     qemu_fdt_setprop_string(mms->fdt, nodename,
 170                             "compatible", "intel,ce4100-ioapic");
 171     qemu_fdt_setprop(mms->fdt, nodename, "interrupt-controller", NULL, 0);
 172     qemu_fdt_setprop_cell(mms->fdt, nodename, "#interrupt-cells", 0x2);
 173     qemu_fdt_setprop_cell(mms->fdt, nodename, "#address-cells", 0x2);
 174     qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg",
 175                                  2, base, 2, 0x1000);
 176
 177     ph = qemu_fdt_alloc_phandle(mms->fdt);
 178     qemu_fdt_setprop_cell(mms->fdt, nodename, "phandle", ph);
 179     qemu_fdt_setprop_cell(mms->fdt, nodename, "linux,phandle", ph);
 180     mms->ioapic_phandle[index] = ph;
 181
 182     g_free(nodename);
 183 }
 184
 185 static void dt_add_isa_serial(MicrovmMachineState *mms, ISADevice *dev)
 186 {
 187     const char compat[] = "ns16550";
 188     uint32_t irq = object_property_get_int(OBJECT(dev), "irq", NULL);
 189     hwaddr base = object_property_get_int(OBJECT(dev), "iobase", NULL);
 190     hwaddr size = 8;
 191     char *nodename;
 192
 193     nodename = g_strdup_printf("/serial@%" PRIx64, base);
 194     qemu_fdt_add_subnode(mms->fdt, nodename);
 195     qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(compat));
 196     qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
 197     dt_add_microvm_irq(mms, nodename, irq);
 198
 199     if (base == 0x3f8 /* com1 */) {
 200         qemu_fdt_setprop_string(mms->fdt, "/chosen", "stdout-path", nodename);
 201     }
 202
 203     g_free(nodename);
 204 }
 205
 206 static void dt_add_isa_rtc(MicrovmMachineState *mms, ISADevice *dev)
 207 {
 208     const char compat[] = "motorola,mc146818";
 209     uint32_t irq = RTC_ISA_IRQ;
 210     hwaddr base = RTC_ISA_BASE;
 211     hwaddr size = 8;
 212     char *nodename;
 213
 214     nodename = g_strdup_printf("/rtc@%" PRIx64, base);
 215     qemu_fdt_add_subnode(mms->fdt, nodename);
 216     qemu_fdt_setprop(mms->fdt, nodename, "compatible", compat, sizeof(compat));
 217     qemu_fdt_setprop_sized_cells(mms->fdt, nodename, "reg", 2, base, 2, size);
 218     dt_add_microvm_irq(mms, nodename, irq);
 219     g_free(nodename);
 220 }
 221
 222 static void dt_setup_isa_bus(MicrovmMachineState *mms, DeviceState *bridge)
 223 {
 224     BusState *bus = qdev_get_child_bus(bridge, "isa.0");
 225     BusChild *kid;
 226     Object *obj;
 227
 228     QTAILQ_FOREACH(kid, &bus->children, sibling) {
 229         DeviceState *dev = kid->child;
 230
 231         /* serial */
 232         obj = object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL);
 233         if (obj) {
 234             dt_add_isa_serial(mms, ISA_DEVICE(obj));
 235             continue;
 236         }
 237
 238         /* rtc */
 239         obj = object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC);
 240         if (obj) {
 241             dt_add_isa_rtc(mms, ISA_DEVICE(obj));
 242             continue;
 243         }
 244
 245         if (debug) {
 246             fprintf(stderr, "%s: unhandled: %s\n", __func__,
 247                     object_get_typename(OBJECT(dev)));
 248         }
 249     }
 250 }
 251
 252 static void dt_setup_sys_bus(MicrovmMachineState *mms)
 253 {
 254     BusState *bus;
 255     BusChild *kid;
 256     Object *obj;
 257
 258     /* sysbus devices */
 259     bus = sysbus_get_default();
 260     QTAILQ_FOREACH(kid, &bus->children, sibling) {
 261         DeviceState *dev = kid->child;
 262
 263         /* ioapic */
 264         obj = object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC);
 265         if (obj) {
 266             dt_add_ioapic(mms, SYS_BUS_DEVICE(obj));
 267             continue;
 268         }
 269     }
 270
 271     QTAILQ_FOREACH(kid, &bus->children, sibling) {
 272         DeviceState *dev = kid->child;
 273
 274         /* virtio */
 275         obj = object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MMIO);
 276         if (obj) {
 277             dt_add_virtio(mms, VIRTIO_MMIO(obj));
 278             continue;
 279         }
 280
 281         /* xhci */
 282         obj = object_dynamic_cast(OBJECT(dev), TYPE_XHCI_SYSBUS);
 283         if (obj) {
 284             dt_add_xhci(mms);
 285             continue;
 286         }
 287
 288         /* pcie */
 289         obj = object_dynamic_cast(OBJECT(dev), TYPE_GPEX_HOST);
 290         if (obj) {
 291             dt_add_pcie(mms);
 292             continue;
 293         }
 294
 295         /* isa */
 296         obj = object_dynamic_cast(OBJECT(dev), "isabus-bridge");
 297         if (obj) {
 298             dt_setup_isa_bus(mms, DEVICE(obj));
 299             continue;
 300         }
 301
 302         if (debug) {
 303             obj = object_dynamic_cast(OBJECT(dev), TYPE_IOAPIC);
 304             if (obj) {
 305                 /* ioapic already added in first pass */
 306                 continue;
 307             }
 308             fprintf(stderr, "%s: unhandled: %s\n", __func__,
 309                     object_get_typename(OBJECT(dev)));
 310         }
 311     }
 312 }
 313
 314 void dt_setup_microvm(MicrovmMachineState *mms)
 315 {
 316     X86MachineState *x86ms = X86_MACHINE(mms);
 317     int size = 0;
 318
 319     mms->fdt = create_device_tree(&size);
 320
 321     /* root node */
 322     qemu_fdt_setprop_string(mms->fdt, "/", "compatible", "linux,microvm");
 323     qemu_fdt_setprop_cell(mms->fdt, "/", "#address-cells", 0x2);
 324     qemu_fdt_setprop_cell(mms->fdt, "/", "#size-cells", 0x2);
 325
 326     qemu_fdt_add_subnode(mms->fdt, "/chosen");
 327     dt_setup_sys_bus(mms);
 328
 329     /* add to fw_cfg */
 330     fprintf(stderr, "%s: add etc/fdt to fw_cfg\n", __func__);
 331     fw_cfg_add_file(x86ms->fw_cfg, "etc/fdt", mms->fdt, size);
 332
 333     if (debug) {
 334         fprintf(stderr, "%s: writing microvm.fdt\n", __func__);
 335         g_file_set_contents("microvm.fdt", mms->fdt, size, NULL);
 336         int ret = system("dtc -I dtb -O dts microvm.fdt");
 337         if (ret != 0) {
 338             fprintf(stderr, "%s: oops, dtc not installed?\n", __func__);
 339         }
 340     }
 341 }