1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
5 #include "tcg/tcg-op.h"
6 #include "tcg/tcg-op-gvec.h"
7 #include "exec/exec-all.h"
8 #include "exec/translator.h"
9 #include "exec/helper-gen.h"
10 #include "internals.h"
11 #include "cpu-features.h"
13 /* internal defines */
16 * Save pc_save across a branch, so that we may restore the value from
17 * before the branch at the point the label is emitted.
19 typedef struct DisasLabel
{
24 typedef struct DisasContext
{
25 DisasContextBase base
;
26 const ARMISARegisters
*isar
;
28 /* The address of the current instruction being translated. */
31 * For CF_PCREL, the full value of cpu_pc is not known
32 * (although the page offset is known). For convenience, the
33 * translation loop uses the full virtual address that triggered
34 * the translation, from base.pc_start through pc_curr.
35 * For efficiency, we do not update cpu_pc for every instruction.
36 * Instead, pc_save has the value of pc_curr at the time of the
37 * last update to cpu_pc, which allows us to compute the addend
38 * needed to bring cpu_pc current: pc_curr - pc_save.
39 * If cpu_pc now contains the destination of an indirect branch,
40 * pc_save contains -1 to indicate that relative updates are no
44 target_ulong page_start
;
46 /* Nonzero if this instruction has been conditionally skipped. */
48 /* The label that will be jumped to when the instruction is skipped. */
50 /* Thumb-2 conditional execution bits. */
53 /* M-profile ECI/ICI exception-continuable instruction state */
56 * trans_ functions for insns which are continuable should set this true
57 * after decode (ie after any UNDEF checks)
62 #if !defined(CONFIG_USER_ONLY)
65 ARMMMUIdx mmu_idx
; /* MMU index to use for normal loads/stores */
66 uint8_t tbii
; /* TBI1|TBI0 for insns */
67 uint8_t tbid
; /* TBI1|TBI0 for data */
68 uint8_t tcma
; /* TCMA1|TCMA0 for MTE */
69 bool ns
; /* Use non-secure CPREG bank on access */
70 int fp_excp_el
; /* FP exception EL or 0 if enabled */
71 int sve_excp_el
; /* SVE exception EL or 0 if enabled */
72 int sme_excp_el
; /* SME exception EL or 0 if enabled */
73 int vl
; /* current vector length in bytes */
74 int svl
; /* current streaming vector length in bytes */
75 bool vfp_enabled
; /* FP enabled via FPSCR.EN */
78 bool v7m_handler_mode
;
79 bool v8m_secure
; /* true if v8M and we're in Secure mode */
80 bool v8m_stackcheck
; /* true if we need to perform v8M stack limit checks */
81 bool v8m_fpccr_s_wrong
; /* true if v8M FPCCR.S != v8m_secure */
82 bool v7m_new_fp_ctxt_needed
; /* ASPEN set but no active FP context */
83 bool v7m_lspact
; /* FPCCR.LSPACT set */
84 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
85 * so that top level loop can generate correct syndrome information.
90 uint64_t features
; /* CPU features bits */
94 /* Because unallocated encodings generate different exception syndrome
95 * information from traps due to FP being disabled, we can't do a single
96 * "is fp access disabled" check at a high level in the decode tree.
97 * To help in catching bugs where the access check was forgotten in some
98 * code path, we set this flag when the access check is done, and assert
99 * that it is set at the point where we actually touch the FP regs.
101 bool fp_access_checked
;
102 bool sve_access_checked
;
103 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
104 * single-step support).
108 /* True if the insn just emitted was a load-exclusive instruction
109 * (necessary for syndrome information for single step exceptions),
110 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
113 /* True if AccType_UNPRIV should be used for LDTR et al */
115 /* True if v8.3-PAuth is active. */
117 /* True if v8.5-MTE access to tags is enabled; index with is_unpriv. */
119 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */
121 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */
123 /* True if any CP15 access is trapped by HSTR_EL2 */
125 /* True if memory operations require alignment */
127 /* True if PSTATE.IL is set */
129 /* True if PSTATE.SM is set. */
131 /* True if PSTATE.ZA is set. */
133 /* True if non-streaming insns should raise an SME Streaming exception. */
134 bool sme_trap_nonstreaming
;
135 /* True if the current instruction is non-streaming. */
136 bool is_nonstreaming
;
137 /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
139 /* True if fine-grained traps are active */
141 /* True if fine-grained trap on SVC is enabled */
143 /* True if a trap on ERET is enabled (FGT or NV) */
145 /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */
147 /* True if FEAT_NV HCR_EL2.NV is enabled */
149 /* True if NV enabled and HCR_EL2.NV1 is set */
151 /* True if NV enabled and HCR_EL2.NV2 is set */
153 /* True if NV2 enabled and NV2 RAM accesses use EL2&0 translation regime */
155 /* True if NV2 enabled and NV2 RAM accesses are big-endian */
158 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
159 * < 0, set by the current instruction.
162 /* A copy of cpu->dcz_blocksize. */
163 uint8_t dcz_blocksize
;
164 /* A copy of cpu->gm_blocksize. */
165 uint8_t gm_blocksize
;
166 /* True if this page is guarded. */
168 /* True if the current insn_start has been updated. */
169 bool insn_start_updated
;
170 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
172 /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */
173 uint32_t nv2_redirect_offset
;
176 typedef struct DisasCompare
{
181 /* Share the TCG temporaries common between 32 and 64 bit modes. */
182 extern TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
183 extern TCGv_i64 cpu_exclusive_addr
;
184 extern TCGv_i64 cpu_exclusive_val
;
187 * Constant expanders for the decoders.
190 static inline int negate(DisasContext
*s
, int x
)
195 static inline int plus_1(DisasContext
*s
, int x
)
200 static inline int plus_2(DisasContext
*s
, int x
)
205 static inline int plus_12(DisasContext
*s
, int x
)
210 static inline int times_2(DisasContext
*s
, int x
)
215 static inline int times_4(DisasContext
*s
, int x
)
220 static inline int times_8(DisasContext
*s
, int x
)
225 static inline int times_2_plus_1(DisasContext
*s
, int x
)
230 static inline int rsub_64(DisasContext
*s
, int x
)
235 static inline int rsub_32(DisasContext
*s
, int x
)
240 static inline int rsub_16(DisasContext
*s
, int x
)
245 static inline int rsub_8(DisasContext
*s
, int x
)
250 static inline int shl_12(DisasContext
*s
, int x
)
255 static inline int xor_2(DisasContext
*s
, int x
)
260 static inline int neon_3same_fp_size(DisasContext
*s
, int x
)
262 /* Convert 0==fp32, 1==fp16 into a MO_* value */
266 static inline int arm_dc_feature(DisasContext
*dc
, int feature
)
268 return (dc
->features
& (1ULL << feature
)) != 0;
271 static inline int get_mem_index(DisasContext
*s
)
273 return arm_to_core_mmu_idx(s
->mmu_idx
);
276 static inline void disas_set_insn_syndrome(DisasContext
*s
, uint32_t syn
)
278 /* We don't need to save all of the syndrome so we mask and shift
279 * out unneeded bits to help the sleb128 encoder do a better job.
281 syn
&= ARM_INSN_START_WORD2_MASK
;
282 syn
>>= ARM_INSN_START_WORD2_SHIFT
;
284 /* Check for multiple updates. */
285 assert(!s
->insn_start_updated
);
286 s
->insn_start_updated
= true;
287 tcg_set_insn_start_param(s
->base
.insn_start
, 2, syn
);
290 static inline int curr_insn_len(DisasContext
*s
)
292 return s
->base
.pc_next
- s
->pc_curr
;
295 /* is_jmp field values */
296 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
297 /* CPU state was modified dynamically; exit to main loop for interrupts. */
298 #define DISAS_UPDATE_EXIT DISAS_TARGET_1
299 /* These instructions trap after executing, so the A32/T32 decoder must
300 * defer them until after the conditional execution state has been updated.
301 * WFI also needs special handling when single-stepping.
303 #define DISAS_WFI DISAS_TARGET_2
304 #define DISAS_SWI DISAS_TARGET_3
306 #define DISAS_WFE DISAS_TARGET_4
307 #define DISAS_HVC DISAS_TARGET_5
308 #define DISAS_SMC DISAS_TARGET_6
309 #define DISAS_YIELD DISAS_TARGET_7
310 /* M profile branch which might be an exception return (and so needs
311 * custom end-of-TB code)
313 #define DISAS_BX_EXCRET DISAS_TARGET_8
315 * For instructions which want an immediate exit to the main loop, as opposed
316 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
317 * doesn't write the PC on exiting the translation loop so you need to ensure
318 * something (gen_a64_update_pc or runtime helper) has done so before we reach
319 * return from cpu_tb_exec.
321 #define DISAS_EXIT DISAS_TARGET_9
322 /* CPU state was modified dynamically; no need to exit, but do not chain. */
323 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10
325 #ifdef TARGET_AARCH64
326 void a64_translate_init(void);
327 void gen_a64_update_pc(DisasContext
*s
, target_long diff
);
328 extern const TranslatorOps aarch64_translator_ops
;
330 static inline void a64_translate_init(void)
334 static inline void gen_a64_update_pc(DisasContext
*s
, target_long diff
)
339 void arm_test_cc(DisasCompare
*cmp
, int cc
);
340 void arm_jump_cc(DisasCompare
*cmp
, TCGLabel
*label
);
341 void arm_gen_test_cc(int cc
, TCGLabel
*label
);
342 MemOp
pow2_align(unsigned i
);
343 void unallocated_encoding(DisasContext
*s
);
344 void gen_exception_insn_el(DisasContext
*s
, target_long pc_diff
, int excp
,
345 uint32_t syn
, uint32_t target_el
);
346 void gen_exception_insn(DisasContext
*s
, target_long pc_diff
,
347 int excp
, uint32_t syn
);
349 /* Return state of Alternate Half-precision flag, caller frees result */
350 static inline TCGv_i32
get_ahp_flag(void)
352 TCGv_i32 ret
= tcg_temp_new_i32();
354 tcg_gen_ld_i32(ret
, tcg_env
,
355 offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPSCR
]));
356 tcg_gen_extract_i32(ret
, ret
, 26, 1);
361 /* Set bits within PSTATE. */
362 static inline void set_pstate_bits(uint32_t bits
)
364 TCGv_i32 p
= tcg_temp_new_i32();
366 tcg_debug_assert(!(bits
& CACHED_PSTATE_BITS
));
368 tcg_gen_ld_i32(p
, tcg_env
, offsetof(CPUARMState
, pstate
));
369 tcg_gen_ori_i32(p
, p
, bits
);
370 tcg_gen_st_i32(p
, tcg_env
, offsetof(CPUARMState
, pstate
));
373 /* Clear bits within PSTATE. */
374 static inline void clear_pstate_bits(uint32_t bits
)
376 TCGv_i32 p
= tcg_temp_new_i32();
378 tcg_debug_assert(!(bits
& CACHED_PSTATE_BITS
));
380 tcg_gen_ld_i32(p
, tcg_env
, offsetof(CPUARMState
, pstate
));
381 tcg_gen_andi_i32(p
, p
, ~bits
);
382 tcg_gen_st_i32(p
, tcg_env
, offsetof(CPUARMState
, pstate
));
385 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
386 static inline void gen_ss_advance(DisasContext
*s
)
390 clear_pstate_bits(PSTATE_SS
);
394 /* Generate an architectural singlestep exception */
395 static inline void gen_swstep_exception(DisasContext
*s
, int isv
, int ex
)
397 /* Fill in the same_el field of the syndrome in the helper. */
398 uint32_t syn
= syn_swstep(false, isv
, ex
);
399 gen_helper_exception_swstep(tcg_env
, tcg_constant_i32(syn
));
403 * Given a VFP floating point constant encoded into an 8 bit immediate in an
404 * instruction, expand it to the actual constant value of the specified
405 * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
407 uint64_t vfp_expand_imm(int size
, uint8_t imm8
);
409 static inline void gen_vfp_absh(TCGv_i32 d
, TCGv_i32 s
)
411 tcg_gen_andi_i32(d
, s
, INT16_MAX
);
414 static inline void gen_vfp_abss(TCGv_i32 d
, TCGv_i32 s
)
416 tcg_gen_andi_i32(d
, s
, INT32_MAX
);
419 static inline void gen_vfp_absd(TCGv_i64 d
, TCGv_i64 s
)
421 tcg_gen_andi_i64(d
, s
, INT64_MAX
);
424 static inline void gen_vfp_negh(TCGv_i32 d
, TCGv_i32 s
)
426 tcg_gen_xori_i32(d
, s
, 1u << 15);
429 static inline void gen_vfp_negs(TCGv_i32 d
, TCGv_i32 s
)
431 tcg_gen_xori_i32(d
, s
, 1u << 31);
434 static inline void gen_vfp_negd(TCGv_i64 d
, TCGv_i64 s
)
436 tcg_gen_xori_i64(d
, s
, 1ull << 63);
439 /* Vector operations shared between ARM and AArch64. */
440 void gen_gvec_ceq0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
441 uint32_t opr_sz
, uint32_t max_sz
);
442 void gen_gvec_clt0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
443 uint32_t opr_sz
, uint32_t max_sz
);
444 void gen_gvec_cgt0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
445 uint32_t opr_sz
, uint32_t max_sz
);
446 void gen_gvec_cle0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
447 uint32_t opr_sz
, uint32_t max_sz
);
448 void gen_gvec_cge0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
449 uint32_t opr_sz
, uint32_t max_sz
);
451 void gen_gvec_mla(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
452 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
453 void gen_gvec_mls(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
454 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
456 void gen_gvec_cmtst(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
457 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
458 void gen_gvec_sshl(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
459 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
460 void gen_gvec_ushl(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
461 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
463 void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
464 void gen_ushl_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
);
465 void gen_sshl_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
);
466 void gen_ushl_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
467 void gen_sshl_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
469 void gen_uqadd_bhs(TCGv_i64 res
, TCGv_i64 qc
,
470 TCGv_i64 a
, TCGv_i64 b
, MemOp esz
);
471 void gen_uqadd_d(TCGv_i64 d
, TCGv_i64 q
, TCGv_i64 a
, TCGv_i64 b
);
472 void gen_gvec_uqadd_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
473 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
475 void gen_sqadd_bhs(TCGv_i64 res
, TCGv_i64 qc
,
476 TCGv_i64 a
, TCGv_i64 b
, MemOp esz
);
477 void gen_sqadd_d(TCGv_i64 d
, TCGv_i64 q
, TCGv_i64 a
, TCGv_i64 b
);
478 void gen_gvec_sqadd_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
479 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
481 void gen_uqsub_bhs(TCGv_i64 res
, TCGv_i64 qc
,
482 TCGv_i64 a
, TCGv_i64 b
, MemOp esz
);
483 void gen_uqsub_d(TCGv_i64 d
, TCGv_i64 q
, TCGv_i64 a
, TCGv_i64 b
);
484 void gen_gvec_uqsub_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
485 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
487 void gen_sqsub_bhs(TCGv_i64 res
, TCGv_i64 qc
,
488 TCGv_i64 a
, TCGv_i64 b
, MemOp esz
);
489 void gen_sqsub_d(TCGv_i64 d
, TCGv_i64 q
, TCGv_i64 a
, TCGv_i64 b
);
490 void gen_gvec_sqsub_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
491 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
493 void gen_gvec_ssra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
494 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
495 void gen_gvec_usra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
496 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
498 void gen_srshr32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
);
499 void gen_srshr64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
);
500 void gen_urshr32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t sh
);
501 void gen_urshr64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t sh
);
503 void gen_gvec_srshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
504 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
505 void gen_gvec_urshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
506 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
507 void gen_gvec_srsra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
508 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
509 void gen_gvec_ursra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
510 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
512 void gen_gvec_sri(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
513 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
514 void gen_gvec_sli(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
515 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
517 void gen_gvec_sqrdmlah_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
518 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
519 void gen_gvec_sqrdmlsh_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
520 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
522 void gen_gvec_sabd(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
523 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
524 void gen_gvec_uabd(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
525 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
527 void gen_gvec_saba(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
528 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
529 void gen_gvec_uaba(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
530 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
532 void gen_gvec_addp(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
533 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
534 void gen_gvec_smaxp(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
535 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
536 void gen_gvec_sminp(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
537 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
538 void gen_gvec_umaxp(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
539 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
540 void gen_gvec_uminp(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
541 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
544 * Forward to the isar_feature_* tests given a DisasContext pointer.
546 #define dc_isar_feature(name, ctx) \
547 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
549 /* Note that the gvec expanders operate on offsets + sizes. */
550 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
551 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
553 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
554 uint32_t, uint32_t, uint32_t);
555 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
556 uint32_t, uint32_t, uint32_t);
558 /* Function prototype for gen_ functions for calling Neon helpers */
559 typedef void NeonGenOneOpFn(TCGv_i32
, TCGv_i32
);
560 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
561 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
562 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
563 typedef void NeonGenThreeOpEnvFn(TCGv_i32
, TCGv_env
, TCGv_i32
,
565 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
566 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
567 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
568 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
569 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
570 typedef void NeonGenTwoOpWidenFn(TCGv_i64
, TCGv_i32
, TCGv_i32
);
571 typedef void NeonGenOneSingleOpFn(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
572 typedef void NeonGenTwoSingleOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
573 typedef void NeonGenTwoDoubleOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
574 typedef void NeonGenOne64OpFn(TCGv_i64
, TCGv_i64
);
575 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
576 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
577 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
578 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, MemOp
);
579 typedef void WideShiftImmFn(TCGv_i64
, TCGv_i64
, int64_t shift
);
580 typedef void WideShiftFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i32
);
581 typedef void ShiftImmFn(TCGv_i32
, TCGv_i32
, int32_t shift
);
582 typedef void ShiftFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
585 * arm_tbflags_from_tb:
586 * @tb: the TranslationBlock
588 * Extract the flag values from @tb.
590 static inline CPUARMTBFlags
arm_tbflags_from_tb(const TranslationBlock
*tb
)
592 return (CPUARMTBFlags
){ tb
->flags
, tb
->cs_base
};
596 * Enum for argument to fpstatus_ptr().
598 typedef enum ARMFPStatusFlavour
{
603 } ARMFPStatusFlavour
;
606 * fpstatus_ptr: return TCGv_ptr to the specified fp_status field
608 * We have multiple softfloat float_status fields in the Arm CPU state struct
609 * (see the comment in cpu.h for details). Return a TCGv_ptr which has
610 * been set up to point to the requested field in the CPU state struct.
614 * for non-FP16 operations controlled by the FPCR
616 * for operations controlled by the FPCR where FPCR.FZ16 is to be used
618 * for A32/T32 Neon operations using the "standard FPSCR value"
620 * as FPST_STD, but where FPCR.FZ16 is to be used
622 static inline TCGv_ptr
fpstatus_ptr(ARMFPStatusFlavour flavour
)
624 TCGv_ptr statusptr
= tcg_temp_new_ptr();
629 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
632 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
635 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status
);
638 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status_f16
);
641 g_assert_not_reached();
643 tcg_gen_addi_ptr(statusptr
, tcg_env
, offset
);
648 * finalize_memop_atom:
650 * @opc: size+sign+align of the memory operation
651 * @atom: atomicity of the memory operation
653 * Build the complete MemOp for a memory operation, including alignment,
654 * endianness, and atomicity.
656 * If (op & MO_AMASK) then the operation already contains the required
657 * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally
658 * unaligned operation, e.g. for AccType_NORMAL.
660 * In the latter case, there are configuration bits that require alignment,
661 * and this is applied here. Note that there is no way to indicate that
662 * no alignment should ever be enforced; this must be handled manually.
664 static inline MemOp
finalize_memop_atom(DisasContext
*s
, MemOp opc
, MemOp atom
)
666 if (s
->align_mem
&& !(opc
& MO_AMASK
)) {
669 return opc
| atom
| s
->be_data
;
675 * @opc: size+sign+align of the memory operation
677 * Like finalize_memop_atom, but with default atomicity.
679 static inline MemOp
finalize_memop(DisasContext
*s
, MemOp opc
)
681 MemOp atom
= s
->lse2
? MO_ATOM_WITHIN16
: MO_ATOM_IFALIGN
;
682 return finalize_memop_atom(s
, opc
, atom
);
686 * finalize_memop_pair:
688 * @opc: size+sign+align of the memory operation
690 * Like finalize_memop_atom, but with atomicity for a pair.
691 * C.f. Pseudocode for Mem[], operand ispair.
693 static inline MemOp
finalize_memop_pair(DisasContext
*s
, MemOp opc
)
695 MemOp atom
= s
->lse2
? MO_ATOM_WITHIN16_PAIR
: MO_ATOM_IFALIGN_PAIR
;
696 return finalize_memop_atom(s
, opc
, atom
);
700 * finalize_memop_asimd:
702 * @opc: size+sign+align of the memory operation
704 * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD.
706 static inline MemOp
finalize_memop_asimd(DisasContext
*s
, MemOp opc
)
709 * In the pseudocode for Mem[], with AccessType_ASIMD, size == 16,
710 * if IsAligned(8), the first case provides separate atomicity for
711 * the pair of 64-bit accesses. If !IsAligned(8), the middle cases
712 * do not apply, and we're left with the final case of no atomicity.
713 * Thus MO_ATOM_IFALIGN_PAIR.
715 * For other sizes, normal LSE2 rules apply.
717 if ((opc
& MO_SIZE
) == MO_128
) {
718 return finalize_memop_atom(s
, opc
, MO_ATOM_IFALIGN_PAIR
);
720 return finalize_memop(s
, opc
);
724 * asimd_imm_const: Expand an encoded SIMD constant value
726 * Expand a SIMD constant value. This is essentially the pseudocode
727 * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
728 * VMVN and VBIC (when cmode < 14 && op == 1).
730 * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
731 * callers must catch this; we return the 64-bit constant value defined
734 * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
735 * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
736 * we produce an immediate constant value of 0 in these cases.
738 uint64_t asimd_imm_const(uint32_t imm
, int cmode
, int op
);
742 * Create a label and cache a copy of pc_save.
744 static inline DisasLabel
gen_disas_label(DisasContext
*s
)
747 .label
= gen_new_label(),
748 .pc_save
= s
->pc_save
,
754 * Emit a label and restore the cached copy of pc_save.
756 static inline void set_disas_label(DisasContext
*s
, DisasLabel l
)
758 gen_set_label(l
.label
);
759 s
->pc_save
= l
.pc_save
;
762 static inline TCGv_ptr
gen_lookup_cp_reg(uint32_t key
)
764 TCGv_ptr ret
= tcg_temp_new_ptr();
765 gen_helper_lookup_cp_reg(ret
, tcg_env
, tcg_constant_i32(key
));
770 * Set and reset rounding mode around another operation.
772 static inline TCGv_i32
gen_set_rmode(ARMFPRounding rmode
, TCGv_ptr fpst
)
774 TCGv_i32
new = tcg_constant_i32(arm_rmode_to_sf(rmode
));
775 TCGv_i32 old
= tcg_temp_new_i32();
777 gen_helper_set_rmode(old
, new, fpst
);
781 static inline void gen_restore_rmode(TCGv_i32 old
, TCGv_ptr fpst
)
783 gen_helper_set_rmode(old
, old
, fpst
);
787 * Helpers for implementing sets of trans_* functions.
788 * Defer the implementation of NAME to FUNC, with optional extra arguments.
790 #define TRANS(NAME, FUNC, ...) \
791 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
792 { return FUNC(s, __VA_ARGS__); }
793 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
794 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
795 { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
797 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \
798 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
800 s->is_nonstreaming = true; \
801 return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \
804 #endif /* TARGET_ARM_TRANSLATE_H */