hw/hppa/dino.c

   1 /*
   2  * HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines
   3  *
   4  * (C) 2017-2019 by Helge Deller <deller@gmx.de>
   5  *
   6  * This work is licensed under the GNU GPL license version 2 or later.
   7  *
   8  * Documentation available at:
   9  * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf
  10  * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qemu/module.h"
  15 #include "qemu/units.h"
  16 #include "qapi/error.h"
  17 #include "cpu.h"
  18 #include "hw/irq.h"
  19 #include "hw/pci/pci.h"
  20 #include "hw/pci/pci_bus.h"
  21 #include "migration/vmstate.h"
  22 #include "hppa_sys.h"
  23 #include "exec/address-spaces.h"
  24 #include "trace.h"
  25
  26
  27 #define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
  28
  29 #define DINO_IAR0               0x004
  30 #define DINO_IODC               0x008
  31 #define DINO_IRR0               0x00C  /* RO */
  32 #define DINO_IAR1               0x010
  33 #define DINO_IRR1               0x014  /* RO */
  34 #define DINO_IMR                0x018
  35 #define DINO_IPR                0x01C
  36 #define DINO_TOC_ADDR           0x020
  37 #define DINO_ICR                0x024
  38 #define DINO_ILR                0x028  /* RO */
  39 #define DINO_IO_COMMAND         0x030  /* WO */
  40 #define DINO_IO_STATUS          0x034  /* RO */
  41 #define DINO_IO_CONTROL         0x038
  42 #define DINO_IO_GSC_ERR_RESP    0x040  /* RO */
  43 #define DINO_IO_ERR_INFO        0x044  /* RO */
  44 #define DINO_IO_PCI_ERR_RESP    0x048  /* RO */
  45 #define DINO_IO_FBB_EN          0x05c
  46 #define DINO_IO_ADDR_EN         0x060
  47 #define DINO_PCI_CONFIG_ADDR    0x064
  48 #define DINO_PCI_CONFIG_DATA    0x068
  49 #define DINO_PCI_IO_DATA        0x06c
  50 #define DINO_PCI_MEM_DATA       0x070  /* Dino 3.x only */
  51 #define DINO_GSC2X_CONFIG       0x7b4  /* RO */
  52 #define DINO_GMASK              0x800
  53 #define DINO_PAMR               0x804
  54 #define DINO_PAPR               0x808
  55 #define DINO_DAMODE             0x80c
  56 #define DINO_PCICMD             0x810
  57 #define DINO_PCISTS             0x814  /* R/WC */
  58 #define DINO_MLTIM              0x81c
  59 #define DINO_BRDG_FEAT          0x820
  60 #define DINO_PCIROR             0x824
  61 #define DINO_PCIWOR             0x828
  62 #define DINO_TLTIM              0x830
  63
  64 #define DINO_IRQS         11      /* bits 0-10 are architected */
  65 #define DINO_IRR_MASK     0x5ff   /* only 10 bits are implemented */
  66 #define DINO_LOCAL_IRQS   (DINO_IRQS + 1)
  67 #define DINO_MASK_IRQ(x)  (1 << (x))
  68
  69 #define PCIINTA   0x001
  70 #define PCIINTB   0x002
  71 #define PCIINTC   0x004
  72 #define PCIINTD   0x008
  73 #define PCIINTE   0x010
  74 #define PCIINTF   0x020
  75 #define GSCEXTINT 0x040
  76 /* #define xxx       0x080 - bit 7 is "default" */
  77 /* #define xxx    0x100 - bit 8 not used */
  78 /* #define xxx    0x200 - bit 9 not used */
  79 #define RS232INT  0x400
  80
  81 #define DINO_MEM_CHUNK_SIZE (8 * MiB)
  82
  83 #define DINO_PCI_HOST_BRIDGE(obj) \
  84     OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
  85
  86 #define DINO800_REGS ((DINO_TLTIM - DINO_GMASK) / 4)
  87 static const uint32_t reg800_keep_bits[DINO800_REGS] = {
  88             MAKE_64BIT_MASK(0, 1),
  89             MAKE_64BIT_MASK(0, 7),
  90             MAKE_64BIT_MASK(0, 7),
  91             MAKE_64BIT_MASK(0, 8),
  92             MAKE_64BIT_MASK(0, 7),
  93             MAKE_64BIT_MASK(0, 9),
  94             MAKE_64BIT_MASK(0, 32),
  95             MAKE_64BIT_MASK(0, 8),
  96             MAKE_64BIT_MASK(0, 30),
  97             MAKE_64BIT_MASK(0, 25),
  98             MAKE_64BIT_MASK(0, 22),
  99             MAKE_64BIT_MASK(0, 9),
 100 };
 101
 102 typedef struct DinoState {
 103     PCIHostState parent_obj;
 104
 105     /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
 106        so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops.  */
 107     uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */
 108
 109     uint32_t iar0;
 110     uint32_t iar1;
 111     uint32_t imr;
 112     uint32_t ipr;
 113     uint32_t icr;
 114     uint32_t ilr;
 115     uint32_t io_fbb_en;
 116     uint32_t io_addr_en;
 117     uint32_t io_control;
 118     uint32_t toc_addr;
 119
 120     uint32_t reg800[DINO800_REGS];
 121
 122     MemoryRegion this_mem;
 123     MemoryRegion pci_mem;
 124     MemoryRegion pci_mem_alias[32];
 125
 126     AddressSpace bm_as;
 127     MemoryRegion bm;
 128     MemoryRegion bm_ram_alias;
 129     MemoryRegion bm_pci_alias;
 130     MemoryRegion bm_cpu_alias;
 131 } DinoState;
 132
 133 /*
 134  * Dino can forward memory accesses from the CPU in the range between
 135  * 0xf0800000 and 0xff000000 to the PCI bus.
 136  */
 137 static void gsc_to_pci_forwarding(DinoState *s)
 138 {
 139     uint32_t io_addr_en, tmp;
 140     int enabled, i;
 141
 142     tmp = extract32(s->io_control, 7, 2);
 143     enabled = (tmp == 0x01);
 144     io_addr_en = s->io_addr_en;
 145     /* Mask out first (=firmware) and last (=Dino) areas. */
 146     io_addr_en &= ~(BIT(31) | BIT(0));
 147
 148     memory_region_transaction_begin();
 149     for (i = 1; i < 31; i++) {
 150         MemoryRegion *mem = &s->pci_mem_alias[i];
 151         if (enabled && (io_addr_en & (1U << i))) {
 152             if (!memory_region_is_mapped(mem)) {
 153                 uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
 154                 memory_region_add_subregion(get_system_memory(), addr, mem);
 155             }
 156         } else if (memory_region_is_mapped(mem)) {
 157             memory_region_del_subregion(get_system_memory(), mem);
 158         }
 159     }
 160     memory_region_transaction_commit();
 161 }
 162
 163 static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
 164                                 unsigned size, bool is_write,
 165                                 MemTxAttrs attrs)
 166 {
 167     bool ret = false;
 168
 169     switch (addr) {
 170     case DINO_IAR0:
 171     case DINO_IAR1:
 172     case DINO_IRR0:
 173     case DINO_IRR1:
 174     case DINO_IMR:
 175     case DINO_IPR:
 176     case DINO_ICR:
 177     case DINO_ILR:
 178     case DINO_IO_CONTROL:
 179     case DINO_IO_FBB_EN:
 180     case DINO_IO_ADDR_EN:
 181     case DINO_PCI_IO_DATA:
 182     case DINO_TOC_ADDR:
 183     case DINO_GMASK ... DINO_TLTIM:
 184         ret = true;
 185         break;
 186     case DINO_PCI_IO_DATA + 2:
 187         ret = (size <= 2);
 188         break;
 189     case DINO_PCI_IO_DATA + 1:
 190     case DINO_PCI_IO_DATA + 3:
 191         ret = (size == 1);
 192     }
 193     trace_dino_chip_mem_valid(addr, ret);
 194     return ret;
 195 }
 196
 197 static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
 198                                              uint64_t *data, unsigned size,
 199                                              MemTxAttrs attrs)
 200 {
 201     DinoState *s = opaque;
 202     MemTxResult ret = MEMTX_OK;
 203     AddressSpace *io;
 204     uint16_t ioaddr;
 205     uint32_t val;
 206
 207     switch (addr) {
 208     case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
 209         /* Read from PCI IO space. */
 210         io = &address_space_io;
 211         ioaddr = s->parent_obj.config_reg + (addr & 3);
 212         switch (size) {
 213         case 1:
 214             val = address_space_ldub(io, ioaddr, attrs, &ret);
 215             break;
 216         case 2:
 217             val = address_space_lduw_be(io, ioaddr, attrs, &ret);
 218             break;
 219         case 4:
 220             val = address_space_ldl_be(io, ioaddr, attrs, &ret);
 221             break;
 222         default:
 223             g_assert_not_reached();
 224         }
 225         break;
 226
 227     case DINO_IO_FBB_EN:
 228         val = s->io_fbb_en;
 229         break;
 230     case DINO_IO_ADDR_EN:
 231         val = s->io_addr_en;
 232         break;
 233     case DINO_IO_CONTROL:
 234         val = s->io_control;
 235         break;
 236
 237     case DINO_IAR0:
 238         val = s->iar0;
 239         break;
 240     case DINO_IAR1:
 241         val = s->iar1;
 242         break;
 243     case DINO_IMR:
 244         val = s->imr;
 245         break;
 246     case DINO_ICR:
 247         val = s->icr;
 248         break;
 249     case DINO_IPR:
 250         val = s->ipr;
 251         /* Any read to IPR clears the register.  */
 252         s->ipr = 0;
 253         break;
 254     case DINO_ILR:
 255         val = s->ilr;
 256         break;
 257     case DINO_IRR0:
 258         val = s->ilr & s->imr & ~s->icr;
 259         break;
 260     case DINO_IRR1:
 261         val = s->ilr & s->imr & s->icr;
 262         break;
 263     case DINO_TOC_ADDR:
 264         val = s->toc_addr;
 265         break;
 266     case DINO_GMASK ... DINO_TLTIM:
 267         val = s->reg800[(addr - DINO_GMASK) / 4];
 268         if (addr == DINO_PAMR) {
 269             val &= ~0x01;  /* LSB is hardwired to 0 */
 270         }
 271         if (addr == DINO_MLTIM) {
 272             val &= ~0x07;  /* 3 LSB are hardwired to 0 */
 273         }
 274         if (addr == DINO_BRDG_FEAT) {
 275             val &= ~(0x10710E0ul | 8); /* bits 5-7, 24 & 15 reserved */
 276         }
 277         break;
 278
 279     default:
 280         /* Controlled by dino_chip_mem_valid above.  */
 281         g_assert_not_reached();
 282     }
 283
 284     trace_dino_chip_read(addr, val);
 285     *data = val;
 286     return ret;
 287 }
 288
 289 static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
 290                                               uint64_t val, unsigned size,
 291                                               MemTxAttrs attrs)
 292 {
 293     DinoState *s = opaque;
 294     AddressSpace *io;
 295     MemTxResult ret;
 296     uint16_t ioaddr;
 297     int i;
 298
 299     trace_dino_chip_write(addr, val);
 300
 301     switch (addr) {
 302     case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
 303         /* Write into PCI IO space.  */
 304         io = &address_space_io;
 305         ioaddr = s->parent_obj.config_reg + (addr & 3);
 306         switch (size) {
 307         case 1:
 308             address_space_stb(io, ioaddr, val, attrs, &ret);
 309             break;
 310         case 2:
 311             address_space_stw_be(io, ioaddr, val, attrs, &ret);
 312             break;
 313         case 4:
 314             address_space_stl_be(io, ioaddr, val, attrs, &ret);
 315             break;
 316         default:
 317             g_assert_not_reached();
 318         }
 319         return ret;
 320
 321     case DINO_IO_FBB_EN:
 322         s->io_fbb_en = val & 0x03;
 323         break;
 324     case DINO_IO_ADDR_EN:
 325         s->io_addr_en = val;
 326         gsc_to_pci_forwarding(s);
 327         break;
 328     case DINO_IO_CONTROL:
 329         s->io_control = val;
 330         gsc_to_pci_forwarding(s);
 331         break;
 332
 333     case DINO_IAR0:
 334         s->iar0 = val;
 335         break;
 336     case DINO_IAR1:
 337         s->iar1 = val;
 338         break;
 339     case DINO_IMR:
 340         s->imr = val;
 341         break;
 342     case DINO_ICR:
 343         s->icr = val;
 344         break;
 345     case DINO_IPR:
 346         /* Any write to IPR clears the register.  */
 347         s->ipr = 0;
 348         break;
 349     case DINO_TOC_ADDR:
 350         /* IO_COMMAND of CPU with client_id bits */
 351         s->toc_addr = 0xFFFA0030 | (val & 0x1e000);
 352         break;
 353
 354     case DINO_ILR:
 355     case DINO_IRR0:
 356     case DINO_IRR1:
 357         /* These registers are read-only.  */
 358         break;
 359
 360     case DINO_GMASK ... DINO_TLTIM:
 361         i = (addr - DINO_GMASK) / 4;
 362         val &= reg800_keep_bits[i];
 363         s->reg800[i] = val;
 364         break;
 365
 366     default:
 367         /* Controlled by dino_chip_mem_valid above.  */
 368         g_assert_not_reached();
 369     }
 370     return MEMTX_OK;
 371 }
 372
 373 static const MemoryRegionOps dino_chip_ops = {
 374     .read_with_attrs = dino_chip_read_with_attrs,
 375     .write_with_attrs = dino_chip_write_with_attrs,
 376     .endianness = DEVICE_BIG_ENDIAN,
 377     .valid = {
 378         .min_access_size = 1,
 379         .max_access_size = 4,
 380         .accepts = dino_chip_mem_valid,
 381     },
 382     .impl = {
 383         .min_access_size = 1,
 384         .max_access_size = 4,
 385     },
 386 };
 387
 388 static const VMStateDescription vmstate_dino = {
 389     .name = "Dino",
 390     .version_id = 2,
 391     .minimum_version_id = 1,
 392     .fields = (VMStateField[]) {
 393         VMSTATE_UINT32(iar0, DinoState),
 394         VMSTATE_UINT32(iar1, DinoState),
 395         VMSTATE_UINT32(imr, DinoState),
 396         VMSTATE_UINT32(ipr, DinoState),
 397         VMSTATE_UINT32(icr, DinoState),
 398         VMSTATE_UINT32(ilr, DinoState),
 399         VMSTATE_UINT32(io_fbb_en, DinoState),
 400         VMSTATE_UINT32(io_addr_en, DinoState),
 401         VMSTATE_UINT32(io_control, DinoState),
 402         VMSTATE_UINT32(toc_addr, DinoState),
 403         VMSTATE_END_OF_LIST()
 404     }
 405 };
 406
 407 /* Unlike pci_config_data_le_ops, no check of high bit set in config_reg.  */
 408
 409 static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
 410 {
 411     PCIHostState *s = opaque;
 412     return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
 413 }
 414
 415 static void dino_config_data_write(void *opaque, hwaddr addr,
 416                                    uint64_t val, unsigned len)
 417 {
 418     PCIHostState *s = opaque;
 419     pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
 420 }
 421
 422 static const MemoryRegionOps dino_config_data_ops = {
 423     .read = dino_config_data_read,
 424     .write = dino_config_data_write,
 425     .endianness = DEVICE_LITTLE_ENDIAN,
 426 };
 427
 428 static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
 429 {
 430     DinoState *s = opaque;
 431     return s->config_reg_dino;
 432 }
 433
 434 static void dino_config_addr_write(void *opaque, hwaddr addr,
 435                                    uint64_t val, unsigned len)
 436 {
 437     PCIHostState *s = opaque;
 438     DinoState *ds = opaque;
 439     ds->config_reg_dino = val; /* keep a copy of original value */
 440     s->config_reg = val & ~3U;
 441 }
 442
 443 static const MemoryRegionOps dino_config_addr_ops = {
 444     .read = dino_config_addr_read,
 445     .write = dino_config_addr_write,
 446     .valid.min_access_size = 4,
 447     .valid.max_access_size = 4,
 448     .endianness = DEVICE_BIG_ENDIAN,
 449 };
 450
 451 static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque,
 452                                             int devfn)
 453 {
 454     DinoState *s = opaque;
 455
 456     return &s->bm_as;
 457 }
 458
 459 /*
 460  * Dino interrupts are connected as shown on Page 78, Table 23
 461  * (Little-endian bit numbers)
 462  *    0   PCI INTA
 463  *    1   PCI INTB
 464  *    2   PCI INTC
 465  *    3   PCI INTD
 466  *    4   PCI INTE
 467  *    5   PCI INTF
 468  *    6   GSC External Interrupt
 469  *    7   Bus Error for "less than fatal" mode
 470  *    8   PS2
 471  *    9   Unused
 472  *    10  RS232
 473  */
 474
 475 static void dino_set_irq(void *opaque, int irq, int level)
 476 {
 477     DinoState *s = opaque;
 478     uint32_t bit = 1u << irq;
 479     uint32_t old_ilr = s->ilr;
 480
 481     if (level) {
 482         uint32_t ena = bit & ~old_ilr;
 483         s->ipr |= ena;
 484         s->ilr = old_ilr | bit;
 485         if (ena & s->imr) {
 486             uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
 487             stl_be_phys(&address_space_memory, iar & -32, iar & 31);
 488         }
 489     } else {
 490         s->ilr = old_ilr & ~bit;
 491     }
 492 }
 493
 494 static int dino_pci_map_irq(PCIDevice *d, int irq_num)
 495 {
 496     int slot = d->devfn >> 3;
 497
 498     assert(irq_num >= 0 && irq_num <= 3);
 499
 500     return slot & 0x03;
 501 }
 502
 503 static void dino_set_timer_irq(void *opaque, int irq, int level)
 504 {
 505     /* ??? Not connected.  */
 506 }
 507
 508 static void dino_set_serial_irq(void *opaque, int irq, int level)
 509 {
 510     dino_set_irq(opaque, 10, level);
 511 }
 512
 513 PCIBus *dino_init(MemoryRegion *addr_space,
 514                   qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq)
 515 {
 516     DeviceState *dev;
 517     DinoState *s;
 518     PCIBus *b;
 519     int i;
 520
 521     dev = qdev_create(NULL, TYPE_DINO_PCI_HOST_BRIDGE);
 522     s = DINO_PCI_HOST_BRIDGE(dev);
 523     s->iar0 = s->iar1 = CPU_HPA + 3;
 524     s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */
 525
 526     /* Dino PCI access from main memory.  */
 527     memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
 528                           s, "dino", 4096);
 529     memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem);
 530
 531     /* Dino PCI config. */
 532     memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj),
 533                           &dino_config_addr_ops, dev, "pci-conf-idx", 4);
 534     memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj),
 535                           &dino_config_data_ops, dev, "pci-conf-data", 4);
 536     memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
 537                                 &s->parent_obj.conf_mem);
 538     memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
 539                                 &s->parent_obj.data_mem);
 540
 541     /* Dino PCI bus memory.  */
 542     memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 1ull << 32);
 543
 544     b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
 545                               &s->pci_mem, get_system_io(),
 546                               PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
 547     s->parent_obj.bus = b;
 548     qdev_init_nofail(dev);
 549
 550     /* Set up windows into PCI bus memory.  */
 551     for (i = 1; i < 31; i++) {
 552         uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
 553         char *name = g_strdup_printf("PCI Outbound Window %d", i);
 554         memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
 555                                  name, &s->pci_mem, addr,
 556                                  DINO_MEM_CHUNK_SIZE);
 557         g_free(name);
 558     }
 559
 560     /* Set up PCI view of memory: Bus master address space.  */
 561     memory_region_init(&s->bm, OBJECT(s), "bm-dino", 1ull << 32);
 562     memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
 563                              "bm-system", addr_space, 0,
 564                              0xf0000000 + DINO_MEM_CHUNK_SIZE);
 565     memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
 566                              "bm-pci", &s->pci_mem,
 567                              0xf0000000 + DINO_MEM_CHUNK_SIZE,
 568                              30 * DINO_MEM_CHUNK_SIZE);
 569     memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s),
 570                              "bm-cpu", addr_space, 0xfff00000,
 571                              0xfffff);
 572     memory_region_add_subregion(&s->bm, 0,
 573                                 &s->bm_ram_alias);
 574     memory_region_add_subregion(&s->bm,
 575                                 0xf0000000 + DINO_MEM_CHUNK_SIZE,
 576                                 &s->bm_pci_alias);
 577     memory_region_add_subregion(&s->bm, 0xfff00000,
 578                                 &s->bm_cpu_alias);
 579     address_space_init(&s->bm_as, &s->bm, "pci-bm");
 580     pci_setup_iommu(b, dino_pcihost_set_iommu, s);
 581
 582     *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0);
 583     *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0);
 584
 585     return b;
 586 }
 587
 588 static void dino_pcihost_class_init(ObjectClass *klass, void *data)
 589 {
 590     DeviceClass *dc = DEVICE_CLASS(klass);
 591
 592     dc->vmsd = &vmstate_dino;
 593 }
 594
 595 static const TypeInfo dino_pcihost_info = {
 596     .name          = TYPE_DINO_PCI_HOST_BRIDGE,
 597     .parent        = TYPE_PCI_HOST_BRIDGE,
 598     .instance_size = sizeof(DinoState),
 599     .class_init    = dino_pcihost_class_init,
 600 };
 601
 602 static void dino_register_types(void)
 603 {
 604     type_register_static(&dino_pcihost_info);
 605 }
 606
 607 type_init(dino_register_types)