2 * Faraday FTGMAC100 Gigabit Ethernet
4 * Copyright (C) 2016-2017, IBM Corporation.
6 * Based on Coldfire Fast Ethernet Controller emulation.
8 * Copyright (c) 2007 CodeSourcery.
10 * This code is licensed under the GPL version 2 or later. See the
11 * COPYING file in the top-level directory.
14 #include "qemu/osdep.h"
15 #include "hw/net/ftgmac100.h"
16 #include "sysemu/dma.h"
18 #include "net/checksum.h"
20 #include "hw/net/mii.h"
28 #define FTGMAC100_ISR 0x00
29 #define FTGMAC100_IER 0x04
30 #define FTGMAC100_MAC_MADR 0x08
31 #define FTGMAC100_MAC_LADR 0x0c
32 #define FTGMAC100_MATH0 0x10
33 #define FTGMAC100_MATH1 0x14
34 #define FTGMAC100_NPTXPD 0x18
35 #define FTGMAC100_RXPD 0x1C
36 #define FTGMAC100_NPTXR_BADR 0x20
37 #define FTGMAC100_RXR_BADR 0x24
38 #define FTGMAC100_HPTXPD 0x28
39 #define FTGMAC100_HPTXR_BADR 0x2c
40 #define FTGMAC100_ITC 0x30
41 #define FTGMAC100_APTC 0x34
42 #define FTGMAC100_DBLAC 0x38
43 #define FTGMAC100_REVR 0x40
44 #define FTGMAC100_FEAR1 0x44
45 #define FTGMAC100_RBSR 0x4c
46 #define FTGMAC100_TPAFCR 0x48
48 #define FTGMAC100_MACCR 0x50
49 #define FTGMAC100_MACSR 0x54
50 #define FTGMAC100_PHYCR 0x60
51 #define FTGMAC100_PHYDATA 0x64
52 #define FTGMAC100_FCR 0x68
55 * Interrupt status register & interrupt enable register
57 #define FTGMAC100_INT_RPKT_BUF (1 << 0)
58 #define FTGMAC100_INT_RPKT_FIFO (1 << 1)
59 #define FTGMAC100_INT_NO_RXBUF (1 << 2)
60 #define FTGMAC100_INT_RPKT_LOST (1 << 3)
61 #define FTGMAC100_INT_XPKT_ETH (1 << 4)
62 #define FTGMAC100_INT_XPKT_FIFO (1 << 5)
63 #define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
64 #define FTGMAC100_INT_XPKT_LOST (1 << 7)
65 #define FTGMAC100_INT_AHB_ERR (1 << 8)
66 #define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
67 #define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
70 * Automatic polling timer control register
72 #define FTGMAC100_APTC_RXPOLL_CNT(x) ((x) & 0xf)
73 #define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
74 #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) >> 8) & 0xf)
75 #define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
78 * PHY control register
80 #define FTGMAC100_PHYCR_MIIRD (1 << 26)
81 #define FTGMAC100_PHYCR_MIIWR (1 << 27)
83 #define FTGMAC100_PHYCR_DEV(x) (((x) >> 16) & 0x1f)
84 #define FTGMAC100_PHYCR_REG(x) (((x) >> 21) & 0x1f)
89 #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
90 #define FTGMAC100_PHYDATA_MIIRDATA(x) (((x) >> 16) & 0xffff)
95 #define FTGMAC100_REVR_NEW_MDIO_INTERFACE (1 << 31)
98 * MAC control register
100 #define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
101 #define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
102 #define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
103 #define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
104 #define FTGMAC100_MACCR_RM_VLAN (1 << 4)
105 #define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
106 #define FTGMAC100_MACCR_LOOP_EN (1 << 6)
107 #define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
108 #define FTGMAC100_MACCR_FULLDUP (1 << 8)
109 #define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
110 #define FTGMAC100_MACCR_CRC_APD (1 << 10) /* not needed */
111 #define FTGMAC100_MACCR_RX_RUNT (1 << 12)
112 #define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
113 #define FTGMAC100_MACCR_RX_ALL (1 << 14)
114 #define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
115 #define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
116 #define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
117 #define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
118 #define FTGMAC100_MACCR_FAST_MODE (1 << 19)
119 #define FTGMAC100_MACCR_SW_RST (1 << 31)
122 * Transmit descriptor
124 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
125 #define FTGMAC100_TXDES0_EDOTR (1 << 15)
126 #define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
127 #define FTGMAC100_TXDES0_LTS (1 << 28)
128 #define FTGMAC100_TXDES0_FTS (1 << 29)
129 #define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
131 #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
132 #define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
133 #define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
134 #define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
135 #define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
136 #define FTGMAC100_TXDES1_LLC (1 << 22)
137 #define FTGMAC100_TXDES1_TX2FIC (1 << 30)
138 #define FTGMAC100_TXDES1_TXIC (1 << 31)
143 #define FTGMAC100_RXDES0_VDBC 0x3fff
144 #define FTGMAC100_RXDES0_EDORR (1 << 15)
145 #define FTGMAC100_RXDES0_MULTICAST (1 << 16)
146 #define FTGMAC100_RXDES0_BROADCAST (1 << 17)
147 #define FTGMAC100_RXDES0_RX_ERR (1 << 18)
148 #define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
149 #define FTGMAC100_RXDES0_FTL (1 << 20)
150 #define FTGMAC100_RXDES0_RUNT (1 << 21)
151 #define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
152 #define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
153 #define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
154 #define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
155 #define FTGMAC100_RXDES0_LRS (1 << 28)
156 #define FTGMAC100_RXDES0_FRS (1 << 29)
157 #define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
159 #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
160 #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
161 #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
162 #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
163 #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
164 #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
165 #define FTGMAC100_RXDES1_LLC (1 << 22)
166 #define FTGMAC100_RXDES1_DF (1 << 23)
167 #define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
168 #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
169 #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
170 #define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
173 * Receive and transmit Buffer Descriptor
178 uint32_t des2
; /* not used by HW */
183 * Specific RTL8211E MII Registers
185 #define RTL8211E_MII_PHYCR 16 /* PHY Specific Control */
186 #define RTL8211E_MII_PHYSR 17 /* PHY Specific Status */
187 #define RTL8211E_MII_INER 18 /* Interrupt Enable */
188 #define RTL8211E_MII_INSR 19 /* Interrupt Status */
189 #define RTL8211E_MII_RXERC 24 /* Receive Error Counter */
190 #define RTL8211E_MII_LDPSR 27 /* Link Down Power Saving */
191 #define RTL8211E_MII_EPAGSR 30 /* Extension Page Select */
192 #define RTL8211E_MII_PAGSEL 31 /* Page Select */
195 * RTL8211E Interrupt Status
197 #define PHY_INT_AUTONEG_ERROR (1 << 15)
198 #define PHY_INT_PAGE_RECV (1 << 12)
199 #define PHY_INT_AUTONEG_COMPLETE (1 << 11)
200 #define PHY_INT_LINK_STATUS (1 << 10)
201 #define PHY_INT_ERROR (1 << 9)
202 #define PHY_INT_DOWN (1 << 8)
203 #define PHY_INT_JABBER (1 << 0)
206 * Max frame size for the receiving buffer
208 #define FTGMAC100_MAX_FRAME_SIZE 10240
210 /* Limits depending on the type of the frame
212 * 9216 for Jumbo frames (+ 4 for VLAN)
213 * 1518 for other frames (+ 4 for VLAN)
215 static int ftgmac100_max_frame_size(FTGMAC100State
*s
)
217 return (s
->maccr
& FTGMAC100_MACCR_JUMBO_LF
? 9216 : 1518) + 4;
220 static void ftgmac100_update_irq(FTGMAC100State
*s
)
222 qemu_set_irq(s
->irq
, s
->isr
& s
->ier
);
226 * The MII phy could raise a GPIO to the processor which in turn
227 * could be handled as an interrpt by the OS.
228 * For now we don't handle any GPIO/interrupt line, so the OS will
229 * have to poll for the PHY status.
231 static void phy_update_irq(FTGMAC100State
*s
)
233 ftgmac100_update_irq(s
);
236 static void phy_update_link(FTGMAC100State
*s
)
238 /* Autonegotiation status mirrors link status. */
239 if (qemu_get_queue(s
->nic
)->link_down
) {
240 s
->phy_status
&= ~(MII_BMSR_LINK_ST
| MII_BMSR_AN_COMP
);
241 s
->phy_int
|= PHY_INT_DOWN
;
243 s
->phy_status
|= (MII_BMSR_LINK_ST
| MII_BMSR_AN_COMP
);
244 s
->phy_int
|= PHY_INT_AUTONEG_COMPLETE
;
249 static void ftgmac100_set_link(NetClientState
*nc
)
251 phy_update_link(FTGMAC100(qemu_get_nic_opaque(nc
)));
254 static void phy_reset(FTGMAC100State
*s
)
256 s
->phy_status
= (MII_BMSR_100TX_FD
| MII_BMSR_100TX_HD
| MII_BMSR_10T_FD
|
257 MII_BMSR_10T_HD
| MII_BMSR_EXTSTAT
| MII_BMSR_MFPS
|
258 MII_BMSR_AN_COMP
| MII_BMSR_AUTONEG
| MII_BMSR_LINK_ST
|
260 s
->phy_control
= (MII_BMCR_AUTOEN
| MII_BMCR_FD
| MII_BMCR_SPEED1000
);
261 s
->phy_advertise
= (MII_ANAR_PAUSE_ASYM
| MII_ANAR_PAUSE
| MII_ANAR_TXFD
|
262 MII_ANAR_TX
| MII_ANAR_10FD
| MII_ANAR_10
|
268 static uint32_t do_phy_read(FTGMAC100State
*s
, int reg
)
273 case MII_BMCR
: /* Basic Control */
274 val
= s
->phy_control
;
276 case MII_BMSR
: /* Basic Status */
279 case MII_PHYID1
: /* ID1 */
280 val
= RTL8211E_PHYID1
;
282 case MII_PHYID2
: /* ID2 */
283 val
= RTL8211E_PHYID2
;
285 case MII_ANAR
: /* Auto-neg advertisement */
286 val
= s
->phy_advertise
;
288 case MII_ANLPAR
: /* Auto-neg Link Partner Ability */
289 val
= (MII_ANLPAR_ACK
| MII_ANLPAR_PAUSE
| MII_ANLPAR_TXFD
|
290 MII_ANLPAR_TX
| MII_ANLPAR_10FD
| MII_ANLPAR_10
|
293 case MII_ANER
: /* Auto-neg Expansion */
296 case MII_CTRL1000
: /* 1000BASE-T control */
297 val
= (MII_CTRL1000_HALF
| MII_CTRL1000_FULL
);
299 case MII_STAT1000
: /* 1000BASE-T status */
300 val
= MII_STAT1000_FULL
;
302 case RTL8211E_MII_INSR
: /* Interrupt status. */
307 case RTL8211E_MII_INER
: /* Interrupt enable */
308 val
= s
->phy_int_mask
;
310 case RTL8211E_MII_PHYCR
:
311 case RTL8211E_MII_PHYSR
:
312 case RTL8211E_MII_RXERC
:
313 case RTL8211E_MII_LDPSR
:
314 case RTL8211E_MII_EPAGSR
:
315 case RTL8211E_MII_PAGSEL
:
316 qemu_log_mask(LOG_UNIMP
, "%s: reg %d not implemented\n",
321 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset %d\n",
330 #define MII_BMCR_MASK (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 | \
331 MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_PDOWN | \
332 MII_BMCR_FD | MII_BMCR_CTST)
333 #define MII_ANAR_MASK 0x2d7f
335 static void do_phy_write(FTGMAC100State
*s
, int reg
, uint32_t val
)
338 case MII_BMCR
: /* Basic Control */
339 if (val
& MII_BMCR_RESET
) {
342 s
->phy_control
= val
& MII_BMCR_MASK
;
343 /* Complete autonegotiation immediately. */
344 if (val
& MII_BMCR_AUTOEN
) {
345 s
->phy_status
|= MII_BMSR_AN_COMP
;
349 case MII_ANAR
: /* Auto-neg advertisement */
350 s
->phy_advertise
= (val
& MII_ANAR_MASK
) | MII_ANAR_TX
;
352 case RTL8211E_MII_INER
: /* Interrupt enable */
353 s
->phy_int_mask
= val
& 0xff;
356 case RTL8211E_MII_PHYCR
:
357 case RTL8211E_MII_PHYSR
:
358 case RTL8211E_MII_RXERC
:
359 case RTL8211E_MII_LDPSR
:
360 case RTL8211E_MII_EPAGSR
:
361 case RTL8211E_MII_PAGSEL
:
362 qemu_log_mask(LOG_UNIMP
, "%s: reg %d not implemented\n",
366 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset %d\n",
372 static int ftgmac100_read_bd(FTGMAC100Desc
*bd
, dma_addr_t addr
)
374 if (dma_memory_read(&address_space_memory
, addr
, bd
, sizeof(*bd
))) {
375 qemu_log_mask(LOG_GUEST_ERROR
, "%s: failed to read descriptor @ 0x%"
376 HWADDR_PRIx
"\n", __func__
, addr
);
379 bd
->des0
= le32_to_cpu(bd
->des0
);
380 bd
->des1
= le32_to_cpu(bd
->des1
);
381 bd
->des2
= le32_to_cpu(bd
->des2
);
382 bd
->des3
= le32_to_cpu(bd
->des3
);
386 static int ftgmac100_write_bd(FTGMAC100Desc
*bd
, dma_addr_t addr
)
390 lebd
.des0
= cpu_to_le32(bd
->des0
);
391 lebd
.des1
= cpu_to_le32(bd
->des1
);
392 lebd
.des2
= cpu_to_le32(bd
->des2
);
393 lebd
.des3
= cpu_to_le32(bd
->des3
);
394 if (dma_memory_write(&address_space_memory
, addr
, &lebd
, sizeof(lebd
))) {
395 qemu_log_mask(LOG_GUEST_ERROR
, "%s: failed to write descriptor @ 0x%"
396 HWADDR_PRIx
"\n", __func__
, addr
);
402 static void ftgmac100_do_tx(FTGMAC100State
*s
, uint32_t tx_ring
,
403 uint32_t tx_descriptor
)
406 uint8_t *ptr
= s
->frame
;
407 uint32_t addr
= tx_descriptor
;
409 int max_frame_size
= ftgmac100_max_frame_size(s
);
415 if (ftgmac100_read_bd(&bd
, addr
) ||
416 ((bd
.des0
& FTGMAC100_TXDES0_TXDMA_OWN
) == 0)) {
417 /* Run out of descriptors to transmit. */
418 s
->isr
|= FTGMAC100_INT_NO_NPTXBUF
;
422 /* record transmit flags as they are valid only on the first
424 if (bd
.des0
& FTGMAC100_TXDES0_FTS
) {
428 len
= bd
.des0
& 0x3FFF;
429 if (frame_size
+ len
> max_frame_size
) {
430 qemu_log_mask(LOG_GUEST_ERROR
, "%s: frame too big : %d bytes\n",
432 len
= max_frame_size
- frame_size
;
435 if (dma_memory_read(&address_space_memory
, bd
.des3
, ptr
, len
)) {
436 qemu_log_mask(LOG_GUEST_ERROR
, "%s: failed to read packet @ 0x%x\n",
438 s
->isr
|= FTGMAC100_INT_NO_NPTXBUF
;
444 if (bd
.des0
& FTGMAC100_TXDES0_LTS
) {
445 if (flags
& FTGMAC100_TXDES1_IP_CHKSUM
) {
446 net_checksum_calculate(s
->frame
, frame_size
);
448 /* Last buffer in frame. */
449 qemu_send_packet(qemu_get_queue(s
->nic
), s
->frame
, frame_size
);
452 if (flags
& FTGMAC100_TXDES1_TXIC
) {
453 s
->isr
|= FTGMAC100_INT_XPKT_ETH
;
457 if (flags
& FTGMAC100_TXDES1_TX2FIC
) {
458 s
->isr
|= FTGMAC100_INT_XPKT_FIFO
;
460 bd
.des0
&= ~FTGMAC100_TXDES0_TXDMA_OWN
;
462 /* Write back the modified descriptor. */
463 ftgmac100_write_bd(&bd
, addr
);
464 /* Advance to the next descriptor. */
465 if (bd
.des0
& FTGMAC100_TXDES0_EDOTR
) {
468 addr
+= sizeof(FTGMAC100Desc
);
472 s
->tx_descriptor
= addr
;
474 ftgmac100_update_irq(s
);
477 static int ftgmac100_can_receive(NetClientState
*nc
)
479 FTGMAC100State
*s
= FTGMAC100(qemu_get_nic_opaque(nc
));
482 if ((s
->maccr
& (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
))
483 != (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
)) {
487 if (ftgmac100_read_bd(&bd
, s
->rx_descriptor
)) {
490 return !(bd
.des0
& FTGMAC100_RXDES0_RXPKT_RDY
);
494 * This is purely informative. The HW can poll the RW (and RX) ring
495 * buffers for available descriptors but we don't need to trigger a
496 * timer for that in qemu.
498 static uint32_t ftgmac100_rxpoll(FTGMAC100State
*s
)
502 * Speed TIME_SEL=0 TIME_SEL=1
504 * 10 51.2 ms 819.2 ms
505 * 100 5.12 ms 81.92 ms
506 * 1000 1.024 ms 16.384 ms
508 static const int div
[] = { 20, 200, 1000 };
510 uint32_t cnt
= 1024 * FTGMAC100_APTC_RXPOLL_CNT(s
->aptcr
);
511 uint32_t speed
= (s
->maccr
& FTGMAC100_MACCR_FAST_MODE
) ? 1 : 0;
514 if (s
->aptcr
& FTGMAC100_APTC_RXPOLL_TIME_SEL
) {
518 if (s
->maccr
& FTGMAC100_MACCR_GIGA_MODE
) {
522 period
= cnt
/ div
[speed
];
527 static void ftgmac100_reset(DeviceState
*d
)
529 FTGMAC100State
*s
= FTGMAC100(d
);
531 /* Reset the FTGMAC100 */
537 s
->rx_descriptor
= 0;
539 s
->tx_descriptor
= 0;
544 s
->dblac
= 0x00022f00;
558 static uint64_t ftgmac100_read(void *opaque
, hwaddr addr
, unsigned size
)
560 FTGMAC100State
*s
= FTGMAC100(opaque
);
562 switch (addr
& 0xff) {
567 case FTGMAC100_MAC_MADR
:
568 return (s
->conf
.macaddr
.a
[0] << 8) | s
->conf
.macaddr
.a
[1];
569 case FTGMAC100_MAC_LADR
:
570 return ((uint32_t) s
->conf
.macaddr
.a
[2] << 24) |
571 (s
->conf
.macaddr
.a
[3] << 16) | (s
->conf
.macaddr
.a
[4] << 8) |
572 s
->conf
.macaddr
.a
[5];
573 case FTGMAC100_MATH0
:
575 case FTGMAC100_MATH1
:
579 case FTGMAC100_DBLAC
:
583 case FTGMAC100_FEAR1
:
585 case FTGMAC100_TPAFCR
:
589 case FTGMAC100_MACCR
:
591 case FTGMAC100_PHYCR
:
593 case FTGMAC100_PHYDATA
:
596 /* We might want to support these one day */
597 case FTGMAC100_HPTXPD
: /* High Priority Transmit Poll Demand */
598 case FTGMAC100_HPTXR_BADR
: /* High Priority Transmit Ring Base Address */
599 case FTGMAC100_MACSR
: /* MAC Status Register (MACSR) */
600 qemu_log_mask(LOG_UNIMP
, "%s: read to unimplemented register 0x%"
601 HWADDR_PRIx
"\n", __func__
, addr
);
604 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset 0x%"
605 HWADDR_PRIx
"\n", __func__
, addr
);
610 static void ftgmac100_write(void *opaque
, hwaddr addr
,
611 uint64_t value
, unsigned size
)
613 FTGMAC100State
*s
= FTGMAC100(opaque
);
616 switch (addr
& 0xff) {
617 case FTGMAC100_ISR
: /* Interrupt status */
620 case FTGMAC100_IER
: /* Interrupt control */
623 case FTGMAC100_MAC_MADR
: /* MAC */
624 s
->conf
.macaddr
.a
[0] = value
>> 8;
625 s
->conf
.macaddr
.a
[1] = value
;
627 case FTGMAC100_MAC_LADR
:
628 s
->conf
.macaddr
.a
[2] = value
>> 24;
629 s
->conf
.macaddr
.a
[3] = value
>> 16;
630 s
->conf
.macaddr
.a
[4] = value
>> 8;
631 s
->conf
.macaddr
.a
[5] = value
;
633 case FTGMAC100_MATH0
: /* Multicast Address Hash Table 0 */
636 case FTGMAC100_MATH1
: /* Multicast Address Hash Table 1 */
639 case FTGMAC100_ITC
: /* TODO: Interrupt Timer Control */
642 case FTGMAC100_RXR_BADR
: /* Ring buffer address */
644 s
->rx_descriptor
= s
->rx_ring
;
647 case FTGMAC100_RBSR
: /* DMA buffer size */
651 case FTGMAC100_NPTXR_BADR
: /* Transmit buffer address */
653 s
->tx_descriptor
= s
->tx_ring
;
656 case FTGMAC100_NPTXPD
: /* Trigger transmit */
657 if ((s
->maccr
& (FTGMAC100_MACCR_TXDMA_EN
| FTGMAC100_MACCR_TXMAC_EN
))
658 == (FTGMAC100_MACCR_TXDMA_EN
| FTGMAC100_MACCR_TXMAC_EN
)) {
659 /* TODO: high priority tx ring */
660 ftgmac100_do_tx(s
, s
->tx_ring
, s
->tx_descriptor
);
662 if (ftgmac100_can_receive(qemu_get_queue(s
->nic
))) {
663 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
667 case FTGMAC100_RXPD
: /* Receive Poll Demand Register */
668 if (ftgmac100_can_receive(qemu_get_queue(s
->nic
))) {
669 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
673 case FTGMAC100_APTC
: /* Automatic polling */
676 if (FTGMAC100_APTC_RXPOLL_CNT(s
->aptcr
)) {
680 if (FTGMAC100_APTC_TXPOLL_CNT(s
->aptcr
)) {
681 qemu_log_mask(LOG_UNIMP
, "%s: no transmit polling\n", __func__
);
685 case FTGMAC100_MACCR
: /* MAC Device control */
687 if (value
& FTGMAC100_MACCR_SW_RST
) {
688 ftgmac100_reset(DEVICE(s
));
691 if (ftgmac100_can_receive(qemu_get_queue(s
->nic
))) {
692 qemu_flush_queued_packets(qemu_get_queue(s
->nic
));
696 case FTGMAC100_PHYCR
: /* PHY Device control */
697 reg
= FTGMAC100_PHYCR_REG(value
);
699 if (value
& FTGMAC100_PHYCR_MIIWR
) {
700 do_phy_write(s
, reg
, s
->phydata
& 0xffff);
701 s
->phycr
&= ~FTGMAC100_PHYCR_MIIWR
;
703 s
->phydata
= do_phy_read(s
, reg
) << 16;
704 s
->phycr
&= ~FTGMAC100_PHYCR_MIIRD
;
707 case FTGMAC100_PHYDATA
:
708 s
->phydata
= value
& 0xffff;
710 case FTGMAC100_DBLAC
: /* DMA Burst Length and Arbitration Control */
713 case FTGMAC100_REVR
: /* Feature Register */
714 /* TODO: Only Old MDIO interface is supported */
715 s
->revr
= value
& ~FTGMAC100_REVR_NEW_MDIO_INTERFACE
;
717 case FTGMAC100_FEAR1
: /* Feature Register 1 */
720 case FTGMAC100_TPAFCR
: /* Transmit Priority Arbitration and FIFO Control */
723 case FTGMAC100_FCR
: /* Flow Control */
727 case FTGMAC100_HPTXPD
: /* High Priority Transmit Poll Demand */
728 case FTGMAC100_HPTXR_BADR
: /* High Priority Transmit Ring Base Address */
729 case FTGMAC100_MACSR
: /* MAC Status Register (MACSR) */
730 qemu_log_mask(LOG_UNIMP
, "%s: write to unimplemented register 0x%"
731 HWADDR_PRIx
"\n", __func__
, addr
);
734 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad address at offset 0x%"
735 HWADDR_PRIx
"\n", __func__
, addr
);
739 ftgmac100_update_irq(s
);
742 static int ftgmac100_filter(FTGMAC100State
*s
, const uint8_t *buf
, size_t len
)
746 if (s
->maccr
& FTGMAC100_MACCR_RX_ALL
) {
750 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf
))) {
752 if (!(s
->maccr
& FTGMAC100_MACCR_RX_BROADPKT
)) {
757 if (!(s
->maccr
& FTGMAC100_MACCR_RX_MULTIPKT
)) {
758 if (!(s
->maccr
& FTGMAC100_MACCR_HT_MULTI_EN
)) {
762 /* TODO: this does not seem to work for ftgmac100 */
763 mcast_idx
= compute_mcast_idx(buf
);
764 if (!(s
->math
[mcast_idx
/ 32] & (1 << (mcast_idx
% 32)))) {
770 if (memcmp(s
->conf
.macaddr
.a
, buf
, 6)) {
779 static ssize_t
ftgmac100_receive(NetClientState
*nc
, const uint8_t *buf
,
782 FTGMAC100State
*s
= FTGMAC100(qemu_get_nic_opaque(nc
));
791 uint32_t first
= FTGMAC100_RXDES0_FRS
;
792 int max_frame_size
= ftgmac100_max_frame_size(s
);
794 if ((s
->maccr
& (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
))
795 != (FTGMAC100_MACCR_RXDMA_EN
| FTGMAC100_MACCR_RXMAC_EN
)) {
799 /* TODO : Pad to minimum Ethernet frame length */
800 /* handle small packets. */
802 qemu_log_mask(LOG_GUEST_ERROR
, "%s: dropped frame of %zd bytes\n",
807 if (size
< 64 && !(s
->maccr
& FTGMAC100_MACCR_RX_RUNT
)) {
808 qemu_log_mask(LOG_GUEST_ERROR
, "%s: dropped runt frame of %zd bytes\n",
813 if (!ftgmac100_filter(s
, buf
, size
)) {
817 /* 4 bytes for the CRC. */
819 crc
= cpu_to_be32(crc32(~0, buf
, size
));
820 crc_ptr
= (uint8_t *) &crc
;
822 /* Huge frames are truncated. */
823 if (size
> max_frame_size
) {
824 size
= max_frame_size
;
825 qemu_log_mask(LOG_GUEST_ERROR
, "%s: frame too big : %zd bytes\n",
827 flags
|= FTGMAC100_RXDES0_FTL
;
830 switch (get_eth_packet_type(PKT_GET_ETH_HDR(buf
))) {
832 flags
|= FTGMAC100_RXDES0_BROADCAST
;
835 flags
|= FTGMAC100_RXDES0_MULTICAST
;
841 addr
= s
->rx_descriptor
;
843 if (!ftgmac100_can_receive(nc
)) {
844 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Unexpected packet\n", __func__
);
848 if (ftgmac100_read_bd(&bd
, addr
) ||
849 (bd
.des0
& FTGMAC100_RXDES0_RXPKT_RDY
)) {
850 /* No descriptors available. Bail out. */
851 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Lost end of frame\n",
853 s
->isr
|= FTGMAC100_INT_NO_RXBUF
;
856 buf_len
= (size
<= s
->rbsr
) ? size
: s
->rbsr
;
857 bd
.des0
|= buf_len
& 0x3fff;
860 /* The last 4 bytes are the CRC. */
865 dma_memory_write(&address_space_memory
, buf_addr
, buf
, buf_len
);
868 dma_memory_write(&address_space_memory
, buf_addr
+ buf_len
,
873 bd
.des0
|= first
| FTGMAC100_RXDES0_RXPKT_RDY
;
876 /* Last buffer in frame. */
877 bd
.des0
|= flags
| FTGMAC100_RXDES0_LRS
;
878 s
->isr
|= FTGMAC100_INT_RPKT_BUF
;
880 s
->isr
|= FTGMAC100_INT_RPKT_FIFO
;
882 ftgmac100_write_bd(&bd
, addr
);
883 if (bd
.des0
& FTGMAC100_RXDES0_EDORR
) {
886 addr
+= sizeof(FTGMAC100Desc
);
889 s
->rx_descriptor
= addr
;
891 ftgmac100_update_irq(s
);
895 static const MemoryRegionOps ftgmac100_ops
= {
896 .read
= ftgmac100_read
,
897 .write
= ftgmac100_write
,
898 .valid
.min_access_size
= 4,
899 .valid
.max_access_size
= 4,
900 .endianness
= DEVICE_LITTLE_ENDIAN
,
903 static void ftgmac100_cleanup(NetClientState
*nc
)
905 FTGMAC100State
*s
= FTGMAC100(qemu_get_nic_opaque(nc
));
910 static NetClientInfo net_ftgmac100_info
= {
911 .type
= NET_CLIENT_DRIVER_NIC
,
912 .size
= sizeof(NICState
),
913 .can_receive
= ftgmac100_can_receive
,
914 .receive
= ftgmac100_receive
,
915 .cleanup
= ftgmac100_cleanup
,
916 .link_status_changed
= ftgmac100_set_link
,
919 static void ftgmac100_realize(DeviceState
*dev
, Error
**errp
)
921 FTGMAC100State
*s
= FTGMAC100(dev
);
922 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
924 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &ftgmac100_ops
, s
,
925 TYPE_FTGMAC100
, 0x2000);
926 sysbus_init_mmio(sbd
, &s
->iomem
);
927 sysbus_init_irq(sbd
, &s
->irq
);
928 qemu_macaddr_default_if_unset(&s
->conf
.macaddr
);
930 s
->conf
.peers
.ncs
[0] = nd_table
[0].netdev
;
932 s
->nic
= qemu_new_nic(&net_ftgmac100_info
, &s
->conf
,
933 object_get_typename(OBJECT(dev
)), DEVICE(dev
)->id
,
935 qemu_format_nic_info_str(qemu_get_queue(s
->nic
), s
->conf
.macaddr
.a
);
937 s
->frame
= g_malloc(FTGMAC100_MAX_FRAME_SIZE
);
940 static const VMStateDescription vmstate_ftgmac100
= {
941 .name
= TYPE_FTGMAC100
,
943 .minimum_version_id
= 1,
944 .fields
= (VMStateField
[]) {
945 VMSTATE_UINT32(irq_state
, FTGMAC100State
),
946 VMSTATE_UINT32(isr
, FTGMAC100State
),
947 VMSTATE_UINT32(ier
, FTGMAC100State
),
948 VMSTATE_UINT32(rx_enabled
, FTGMAC100State
),
949 VMSTATE_UINT32(rx_ring
, FTGMAC100State
),
950 VMSTATE_UINT32(rbsr
, FTGMAC100State
),
951 VMSTATE_UINT32(tx_ring
, FTGMAC100State
),
952 VMSTATE_UINT32(rx_descriptor
, FTGMAC100State
),
953 VMSTATE_UINT32(tx_descriptor
, FTGMAC100State
),
954 VMSTATE_UINT32_ARRAY(math
, FTGMAC100State
, 2),
955 VMSTATE_UINT32(itc
, FTGMAC100State
),
956 VMSTATE_UINT32(aptcr
, FTGMAC100State
),
957 VMSTATE_UINT32(dblac
, FTGMAC100State
),
958 VMSTATE_UINT32(revr
, FTGMAC100State
),
959 VMSTATE_UINT32(fear1
, FTGMAC100State
),
960 VMSTATE_UINT32(tpafcr
, FTGMAC100State
),
961 VMSTATE_UINT32(maccr
, FTGMAC100State
),
962 VMSTATE_UINT32(phycr
, FTGMAC100State
),
963 VMSTATE_UINT32(phydata
, FTGMAC100State
),
964 VMSTATE_UINT32(fcr
, FTGMAC100State
),
965 VMSTATE_UINT32(phy_status
, FTGMAC100State
),
966 VMSTATE_UINT32(phy_control
, FTGMAC100State
),
967 VMSTATE_UINT32(phy_advertise
, FTGMAC100State
),
968 VMSTATE_UINT32(phy_int
, FTGMAC100State
),
969 VMSTATE_UINT32(phy_int_mask
, FTGMAC100State
),
970 VMSTATE_END_OF_LIST()
974 static Property ftgmac100_properties
[] = {
975 DEFINE_NIC_PROPERTIES(FTGMAC100State
, conf
),
976 DEFINE_PROP_END_OF_LIST(),
979 static void ftgmac100_class_init(ObjectClass
*klass
, void *data
)
981 DeviceClass
*dc
= DEVICE_CLASS(klass
);
983 dc
->vmsd
= &vmstate_ftgmac100
;
984 dc
->reset
= ftgmac100_reset
;
985 dc
->props
= ftgmac100_properties
;
986 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
987 dc
->realize
= ftgmac100_realize
;
988 dc
->desc
= "Faraday FTGMAC100 Gigabit Ethernet emulation";
991 static const TypeInfo ftgmac100_info
= {
992 .name
= TYPE_FTGMAC100
,
993 .parent
= TYPE_SYS_BUS_DEVICE
,
994 .instance_size
= sizeof(FTGMAC100State
),
995 .class_init
= ftgmac100_class_init
,
998 static void ftgmac100_register_types(void)
1000 type_register_static(&ftgmac100_info
);
1003 type_init(ftgmac100_register_types
)