2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/error-report.h"
25 #include "sysemu/hw_accel.h"
27 #include "mmu-hash64.h"
30 #include "mmu-book3s-v3.h"
35 # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
37 # define LOG_SLB(...) do { } while (0)
44 static ppc_slb_t
*slb_lookup(PowerPCCPU
*cpu
, target_ulong eaddr
)
46 CPUPPCState
*env
= &cpu
->env
;
47 uint64_t esid_256M
, esid_1T
;
50 LOG_SLB("%s: eaddr " TARGET_FMT_lx
"\n", __func__
, eaddr
);
52 esid_256M
= (eaddr
& SEGMENT_MASK_256M
) | SLB_ESID_V
;
53 esid_1T
= (eaddr
& SEGMENT_MASK_1T
) | SLB_ESID_V
;
55 for (n
= 0; n
< env
->slb_nr
; n
++) {
56 ppc_slb_t
*slb
= &env
->slb
[n
];
58 LOG_SLB("%s: slot %d %016" PRIx64
" %016"
59 PRIx64
"\n", __func__
, n
, slb
->esid
, slb
->vsid
);
60 /* We check for 1T matches on all MMUs here - if the MMU
61 * doesn't have 1T segment support, we will have prevented 1T
62 * entries from being inserted in the slbmte code. */
63 if (((slb
->esid
== esid_256M
) &&
64 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_256M
))
65 || ((slb
->esid
== esid_1T
) &&
66 ((slb
->vsid
& SLB_VSID_B
) == SLB_VSID_B_1T
))) {
74 void dump_slb(FILE *f
, fprintf_function cpu_fprintf
, PowerPCCPU
*cpu
)
76 CPUPPCState
*env
= &cpu
->env
;
80 cpu_synchronize_state(CPU(cpu
));
82 cpu_fprintf(f
, "SLB\tESID\t\t\tVSID\n");
83 for (i
= 0; i
< env
->slb_nr
; i
++) {
84 slbe
= env
->slb
[i
].esid
;
85 slbv
= env
->slb
[i
].vsid
;
86 if (slbe
== 0 && slbv
== 0) {
89 cpu_fprintf(f
, "%d\t0x%016" PRIx64
"\t0x%016" PRIx64
"\n",
94 void helper_slbia(CPUPPCState
*env
)
98 /* XXX: Warning: slbia never invalidates the first segment */
99 for (n
= 1; n
< env
->slb_nr
; n
++) {
100 ppc_slb_t
*slb
= &env
->slb
[n
];
102 if (slb
->esid
& SLB_ESID_V
) {
103 slb
->esid
&= ~SLB_ESID_V
;
104 /* XXX: given the fact that segment size is 256 MB or 1TB,
105 * and we still don't have a tlb_flush_mask(env, n, mask)
106 * in QEMU, we just invalidate all TLBs
108 env
->tlb_need_flush
|= TLB_NEED_LOCAL_FLUSH
;
113 static void __helper_slbie(CPUPPCState
*env
, target_ulong addr
,
116 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
119 slb
= slb_lookup(cpu
, addr
);
124 if (slb
->esid
& SLB_ESID_V
) {
125 slb
->esid
&= ~SLB_ESID_V
;
127 /* XXX: given the fact that segment size is 256 MB or 1TB,
128 * and we still don't have a tlb_flush_mask(env, n, mask)
129 * in QEMU, we just invalidate all TLBs
131 env
->tlb_need_flush
|=
132 (global
== false ? TLB_NEED_LOCAL_FLUSH
: TLB_NEED_GLOBAL_FLUSH
);
136 void helper_slbie(CPUPPCState
*env
, target_ulong addr
)
138 __helper_slbie(env
, addr
, false);
141 void helper_slbieg(CPUPPCState
*env
, target_ulong addr
)
143 __helper_slbie(env
, addr
, true);
146 int ppc_store_slb(PowerPCCPU
*cpu
, target_ulong slot
,
147 target_ulong esid
, target_ulong vsid
)
149 CPUPPCState
*env
= &cpu
->env
;
150 ppc_slb_t
*slb
= &env
->slb
[slot
];
151 const PPCHash64SegmentPageSizes
*sps
= NULL
;
154 if (slot
>= env
->slb_nr
) {
155 return -1; /* Bad slot number */
157 if (esid
& ~(SLB_ESID_ESID
| SLB_ESID_V
)) {
158 return -1; /* Reserved bits set */
160 if (vsid
& (SLB_VSID_B
& ~SLB_VSID_B_1T
)) {
161 return -1; /* Bad segment size */
163 if ((vsid
& SLB_VSID_B
) && !(env
->mmu_model
& POWERPC_MMU_1TSEG
)) {
164 return -1; /* 1T segment on MMU that doesn't support it */
167 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
168 const PPCHash64SegmentPageSizes
*sps1
= &cpu
->hash64_opts
->sps
[i
];
170 if (!sps1
->page_shift
) {
174 if ((vsid
& SLB_VSID_LLP_MASK
) == sps1
->slb_enc
) {
181 error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu
182 " esid 0x"TARGET_FMT_lx
" vsid 0x"TARGET_FMT_lx
,
191 LOG_SLB("%s: " TARGET_FMT_lu
" " TARGET_FMT_lx
" - " TARGET_FMT_lx
192 " => %016" PRIx64
" %016" PRIx64
"\n", __func__
, slot
, esid
, vsid
,
193 slb
->esid
, slb
->vsid
);
198 static int ppc_load_slb_esid(PowerPCCPU
*cpu
, target_ulong rb
,
201 CPUPPCState
*env
= &cpu
->env
;
202 int slot
= rb
& 0xfff;
203 ppc_slb_t
*slb
= &env
->slb
[slot
];
205 if (slot
>= env
->slb_nr
) {
213 static int ppc_load_slb_vsid(PowerPCCPU
*cpu
, target_ulong rb
,
216 CPUPPCState
*env
= &cpu
->env
;
217 int slot
= rb
& 0xfff;
218 ppc_slb_t
*slb
= &env
->slb
[slot
];
220 if (slot
>= env
->slb_nr
) {
228 static int ppc_find_slb_vsid(PowerPCCPU
*cpu
, target_ulong rb
,
231 CPUPPCState
*env
= &cpu
->env
;
234 if (!msr_is_64bit(env
, env
->msr
)) {
237 slb
= slb_lookup(cpu
, rb
);
239 *rt
= (target_ulong
)-1ul;
246 void helper_store_slb(CPUPPCState
*env
, target_ulong rb
, target_ulong rs
)
248 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
250 if (ppc_store_slb(cpu
, rb
& 0xfff, rb
& ~0xfffULL
, rs
) < 0) {
251 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
252 POWERPC_EXCP_INVAL
, GETPC());
256 target_ulong
helper_load_slb_esid(CPUPPCState
*env
, target_ulong rb
)
258 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
261 if (ppc_load_slb_esid(cpu
, rb
, &rt
) < 0) {
262 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
263 POWERPC_EXCP_INVAL
, GETPC());
268 target_ulong
helper_find_slb_vsid(CPUPPCState
*env
, target_ulong rb
)
270 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
273 if (ppc_find_slb_vsid(cpu
, rb
, &rt
) < 0) {
274 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
275 POWERPC_EXCP_INVAL
, GETPC());
280 target_ulong
helper_load_slb_vsid(CPUPPCState
*env
, target_ulong rb
)
282 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
285 if (ppc_load_slb_vsid(cpu
, rb
, &rt
) < 0) {
286 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
287 POWERPC_EXCP_INVAL
, GETPC());
292 /* Check No-Execute or Guarded Storage */
293 static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU
*cpu
,
294 ppc_hash_pte64_t pte
)
296 /* Exec permissions CANNOT take away read or write permissions */
297 return (pte
.pte1
& HPTE64_R_N
) || (pte
.pte1
& HPTE64_R_G
) ?
298 PAGE_READ
| PAGE_WRITE
: PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
301 /* Check Basic Storage Protection */
302 static int ppc_hash64_pte_prot(PowerPCCPU
*cpu
,
303 ppc_slb_t
*slb
, ppc_hash_pte64_t pte
)
305 CPUPPCState
*env
= &cpu
->env
;
307 /* Some pp bit combinations have undefined behaviour, so default
308 * to no access in those cases */
311 key
= !!(msr_pr
? (slb
->vsid
& SLB_VSID_KP
)
312 : (slb
->vsid
& SLB_VSID_KS
));
313 pp
= (pte
.pte1
& HPTE64_R_PP
) | ((pte
.pte1
& HPTE64_R_PP0
) >> 61);
320 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
325 prot
= PAGE_READ
| PAGE_EXEC
;
336 prot
= PAGE_READ
| PAGE_EXEC
;
340 prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
348 /* Check the instruction access permissions specified in the IAMR */
349 static int ppc_hash64_iamr_prot(PowerPCCPU
*cpu
, int key
)
351 CPUPPCState
*env
= &cpu
->env
;
352 int iamr_bits
= (env
->spr
[SPR_IAMR
] >> 2 * (31 - key
)) & 0x3;
355 * An instruction fetch is permitted if the IAMR bit is 0.
356 * If the bit is set, return PAGE_READ | PAGE_WRITE because this bit
357 * can only take away EXEC permissions not READ or WRITE permissions.
358 * If bit is cleared return PAGE_READ | PAGE_WRITE | PAGE_EXEC since
359 * EXEC permissions are allowed.
361 return (iamr_bits
& 0x1) ? PAGE_READ
| PAGE_WRITE
:
362 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
365 static int ppc_hash64_amr_prot(PowerPCCPU
*cpu
, ppc_hash_pte64_t pte
)
367 CPUPPCState
*env
= &cpu
->env
;
369 int prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
371 /* Only recent MMUs implement Virtual Page Class Key Protection */
372 if (!(env
->mmu_model
& POWERPC_MMU_AMR
)) {
376 key
= HPTE64_R_KEY(pte
.pte1
);
377 amrbits
= (env
->spr
[SPR_AMR
] >> 2*(31 - key
)) & 0x3;
379 /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */
380 /* env->spr[SPR_AMR]); */
383 * A store is permitted if the AMR bit is 0. Remove write
384 * protection if it is set.
390 * A load is permitted if the AMR bit is 0. Remove read
391 * protection if it is set.
397 switch (env
->mmu_model
) {
399 * MMU version 2.07 and later support IAMR
400 * Check if the IAMR allows the instruction access - it will return
401 * PAGE_EXEC if it doesn't (and thus that bit will be cleared) or 0
402 * if it does (and prot will be unchanged indicating execution support).
404 case POWERPC_MMU_2_07
:
405 case POWERPC_MMU_3_00
:
406 prot
&= ppc_hash64_iamr_prot(cpu
, key
);
415 const ppc_hash_pte64_t
*ppc_hash64_map_hptes(PowerPCCPU
*cpu
,
418 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
419 hwaddr base
= ppc_hash64_hpt_base(cpu
);
420 hwaddr plen
= n
* HASH_PTE_SIZE_64
;
421 const ppc_hash_pte64_t
*hptes
;
424 PPCVirtualHypervisorClass
*vhc
=
425 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
426 return vhc
->map_hptes(cpu
->vhyp
, ptex
, n
);
433 hptes
= address_space_map(CPU(cpu
)->as
, base
+ pte_offset
, &plen
, false);
434 if (plen
< (n
* HASH_PTE_SIZE_64
)) {
435 hw_error("%s: Unable to map all requested HPTEs\n", __func__
);
440 void ppc_hash64_unmap_hptes(PowerPCCPU
*cpu
, const ppc_hash_pte64_t
*hptes
,
444 PPCVirtualHypervisorClass
*vhc
=
445 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
446 vhc
->unmap_hptes(cpu
->vhyp
, hptes
, ptex
, n
);
450 address_space_unmap(CPU(cpu
)->as
, (void *)hptes
, n
* HASH_PTE_SIZE_64
,
451 false, n
* HASH_PTE_SIZE_64
);
454 static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes
*sps
,
455 uint64_t pte0
, uint64_t pte1
)
459 if (!(pte0
& HPTE64_V_LARGE
)) {
460 if (sps
->page_shift
!= 12) {
461 /* 4kiB page in a non 4kiB segment */
464 /* Normal 4kiB page */
468 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
469 const PPCHash64PageSize
*ps
= &sps
->enc
[i
];
472 if (!ps
->page_shift
) {
476 if (ps
->page_shift
== 12) {
477 /* L bit is set so this can't be a 4kiB page */
481 mask
= ((1ULL << ps
->page_shift
) - 1) & HPTE64_R_RPN
;
483 if ((pte1
& mask
) == ((uint64_t)ps
->pte_enc
<< HPTE64_R_RPN_SHIFT
)) {
484 return ps
->page_shift
;
488 return 0; /* Bad page size encoding */
491 static hwaddr
ppc_hash64_pteg_search(PowerPCCPU
*cpu
, hwaddr hash
,
492 const PPCHash64SegmentPageSizes
*sps
,
494 ppc_hash_pte64_t
*pte
, unsigned *pshift
)
497 const ppc_hash_pte64_t
*pteg
;
498 target_ulong pte0
, pte1
;
501 ptex
= (hash
& ppc_hash64_hpt_mask(cpu
)) * HPTES_PER_GROUP
;
502 pteg
= ppc_hash64_map_hptes(cpu
, ptex
, HPTES_PER_GROUP
);
506 for (i
= 0; i
< HPTES_PER_GROUP
; i
++) {
507 pte0
= ppc_hash64_hpte0(cpu
, pteg
, i
);
508 pte1
= ppc_hash64_hpte1(cpu
, pteg
, i
);
510 /* This compares V, B, H (secondary) and the AVPN */
511 if (HPTE64_V_COMPARE(pte0
, ptem
)) {
512 *pshift
= hpte_page_shift(sps
, pte0
, pte1
);
514 * If there is no match, ignore the PTE, it could simply
515 * be for a different segment size encoding and the
516 * architecture specifies we should not match. Linux will
517 * potentially leave behind PTEs for the wrong base page
518 * size when demoting segments.
523 /* We don't do anything with pshift yet as qemu TLB only deals
524 * with 4K pages anyway
528 ppc_hash64_unmap_hptes(cpu
, pteg
, ptex
, HPTES_PER_GROUP
);
532 ppc_hash64_unmap_hptes(cpu
, pteg
, ptex
, HPTES_PER_GROUP
);
534 * We didn't find a valid entry.
539 static hwaddr
ppc_hash64_htab_lookup(PowerPCCPU
*cpu
,
540 ppc_slb_t
*slb
, target_ulong eaddr
,
541 ppc_hash_pte64_t
*pte
, unsigned *pshift
)
543 CPUPPCState
*env
= &cpu
->env
;
545 uint64_t vsid
, epnmask
, epn
, ptem
;
546 const PPCHash64SegmentPageSizes
*sps
= slb
->sps
;
548 /* The SLB store path should prevent any bad page size encodings
549 * getting in there, so: */
552 /* If ISL is set in LPCR we need to clamp the page size to 4K */
553 if (env
->spr
[SPR_LPCR
] & LPCR_ISL
) {
554 /* We assume that when using TCG, 4k is first entry of SPS */
555 sps
= &cpu
->hash64_opts
->sps
[0];
556 assert(sps
->page_shift
== 12);
559 epnmask
= ~((1ULL << sps
->page_shift
) - 1);
561 if (slb
->vsid
& SLB_VSID_B
) {
563 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT_1T
;
564 epn
= (eaddr
& ~SEGMENT_MASK_1T
) & epnmask
;
565 hash
= vsid
^ (vsid
<< 25) ^ (epn
>> sps
->page_shift
);
568 vsid
= (slb
->vsid
& SLB_VSID_VSID
) >> SLB_VSID_SHIFT
;
569 epn
= (eaddr
& ~SEGMENT_MASK_256M
) & epnmask
;
570 hash
= vsid
^ (epn
>> sps
->page_shift
);
572 ptem
= (slb
->vsid
& SLB_VSID_PTEM
) | ((epn
>> 16) & HPTE64_V_AVPN
);
573 ptem
|= HPTE64_V_VALID
;
575 /* Page address translation */
576 qemu_log_mask(CPU_LOG_MMU
,
577 "htab_base " TARGET_FMT_plx
" htab_mask " TARGET_FMT_plx
578 " hash " TARGET_FMT_plx
"\n",
579 ppc_hash64_hpt_base(cpu
), ppc_hash64_hpt_mask(cpu
), hash
);
581 /* Primary PTEG lookup */
582 qemu_log_mask(CPU_LOG_MMU
,
583 "0 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
584 " vsid=" TARGET_FMT_lx
" ptem=" TARGET_FMT_lx
585 " hash=" TARGET_FMT_plx
"\n",
586 ppc_hash64_hpt_base(cpu
), ppc_hash64_hpt_mask(cpu
),
588 ptex
= ppc_hash64_pteg_search(cpu
, hash
, sps
, ptem
, pte
, pshift
);
591 /* Secondary PTEG lookup */
592 ptem
|= HPTE64_V_SECONDARY
;
593 qemu_log_mask(CPU_LOG_MMU
,
594 "1 htab=" TARGET_FMT_plx
"/" TARGET_FMT_plx
595 " vsid=" TARGET_FMT_lx
" api=" TARGET_FMT_lx
596 " hash=" TARGET_FMT_plx
"\n", ppc_hash64_hpt_base(cpu
),
597 ppc_hash64_hpt_mask(cpu
), vsid
, ptem
, ~hash
);
599 ptex
= ppc_hash64_pteg_search(cpu
, ~hash
, sps
, ptem
, pte
, pshift
);
605 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU
*cpu
,
606 uint64_t pte0
, uint64_t pte1
)
610 if (!(pte0
& HPTE64_V_LARGE
)) {
615 * The encodings in env->sps need to be carefully chosen so that
616 * this gives an unambiguous result.
618 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
619 const PPCHash64SegmentPageSizes
*sps
= &cpu
->hash64_opts
->sps
[i
];
622 if (!sps
->page_shift
) {
626 shift
= hpte_page_shift(sps
, pte0
, pte1
);
635 static void ppc_hash64_set_isi(CPUState
*cs
, uint64_t error_code
)
637 CPUPPCState
*env
= &POWERPC_CPU(cs
)->env
;
641 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM1
);
643 switch (env
->mmu_model
) {
644 case POWERPC_MMU_3_00
:
645 /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
649 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM0
);
653 if (vpm
&& !msr_hv
) {
654 cs
->exception_index
= POWERPC_EXCP_HISI
;
656 cs
->exception_index
= POWERPC_EXCP_ISI
;
658 env
->error_code
= error_code
;
661 static void ppc_hash64_set_dsi(CPUState
*cs
, uint64_t dar
, uint64_t dsisr
)
663 CPUPPCState
*env
= &POWERPC_CPU(cs
)->env
;
667 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM1
);
669 switch (env
->mmu_model
) {
670 case POWERPC_MMU_3_00
:
671 /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
675 vpm
= !!(env
->spr
[SPR_LPCR
] & LPCR_VPM0
);
679 if (vpm
&& !msr_hv
) {
680 cs
->exception_index
= POWERPC_EXCP_HDSI
;
681 env
->spr
[SPR_HDAR
] = dar
;
682 env
->spr
[SPR_HDSISR
] = dsisr
;
684 cs
->exception_index
= POWERPC_EXCP_DSI
;
685 env
->spr
[SPR_DAR
] = dar
;
686 env
->spr
[SPR_DSISR
] = dsisr
;
692 int ppc_hash64_handle_mmu_fault(PowerPCCPU
*cpu
, vaddr eaddr
,
693 int rwx
, int mmu_idx
)
695 CPUState
*cs
= CPU(cpu
);
696 CPUPPCState
*env
= &cpu
->env
;
700 ppc_hash_pte64_t pte
;
701 int exec_prot
, pp_prot
, amr_prot
, prot
;
703 const int need_prot
[] = {PAGE_READ
, PAGE_WRITE
, PAGE_EXEC
};
706 assert((rwx
== 0) || (rwx
== 1) || (rwx
== 2));
708 /* Note on LPCR usage: 970 uses HID4, but our special variant
709 * of store_spr copies relevant fields into env->spr[SPR_LPCR].
710 * Similarily we filter unimplemented bits when storing into
711 * LPCR depending on the MMU version. This code can thus just
712 * use the LPCR "as-is".
715 /* 1. Handle real mode accesses */
716 if (((rwx
== 2) && (msr_ir
== 0)) || ((rwx
!= 2) && (msr_dr
== 0))) {
717 /* Translation is supposedly "off" */
718 /* In real mode the top 4 effective address bits are (mostly) ignored */
719 raddr
= eaddr
& 0x0FFFFFFFFFFFFFFFULL
;
721 /* In HV mode, add HRMOR if top EA bit is clear */
722 if (msr_hv
|| !env
->has_hv_mode
) {
723 if (!(eaddr
>> 63)) {
724 raddr
|= env
->spr
[SPR_HRMOR
];
727 /* Otherwise, check VPM for RMA vs VRMA */
728 if (env
->spr
[SPR_LPCR
] & LPCR_VPM0
) {
729 slb
= &env
->vrma_slb
;
731 goto skip_slb_search
;
733 /* Not much else to do here */
734 cs
->exception_index
= POWERPC_EXCP_MCHECK
;
737 } else if (raddr
< env
->rmls
) {
738 /* RMA. Check bounds in RMLS */
739 raddr
|= env
->spr
[SPR_RMOR
];
741 /* The access failed, generate the approriate interrupt */
743 ppc_hash64_set_isi(cs
, SRR1_PROTFAULT
);
745 int dsisr
= DSISR_PROTFAULT
;
747 dsisr
|= DSISR_ISSTORE
;
749 ppc_hash64_set_dsi(cs
, eaddr
, dsisr
);
754 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
755 PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
, mmu_idx
,
760 /* 2. Translation is on, so look up the SLB */
761 slb
= slb_lookup(cpu
, eaddr
);
763 /* No entry found, check if in-memory segment tables are in use */
764 if ((env
->mmu_model
& POWERPC_MMU_V3
) && ppc64_use_proc_tbl(cpu
)) {
765 /* TODO - Unsupported */
766 error_report("Segment Table Support Unimplemented");
769 /* Segment still not found, generate the appropriate interrupt */
771 cs
->exception_index
= POWERPC_EXCP_ISEG
;
774 cs
->exception_index
= POWERPC_EXCP_DSEG
;
776 env
->spr
[SPR_DAR
] = eaddr
;
783 /* 3. Check for segment level no-execute violation */
784 if ((rwx
== 2) && (slb
->vsid
& SLB_VSID_N
)) {
785 ppc_hash64_set_isi(cs
, SRR1_NOEXEC_GUARD
);
789 /* 4. Locate the PTE in the hash table */
790 ptex
= ppc_hash64_htab_lookup(cpu
, slb
, eaddr
, &pte
, &apshift
);
793 ppc_hash64_set_isi(cs
, SRR1_NOPTE
);
795 int dsisr
= DSISR_NOPTE
;
797 dsisr
|= DSISR_ISSTORE
;
799 ppc_hash64_set_dsi(cs
, eaddr
, dsisr
);
803 qemu_log_mask(CPU_LOG_MMU
,
804 "found PTE at index %08" HWADDR_PRIx
"\n", ptex
);
806 /* 5. Check access permissions */
808 exec_prot
= ppc_hash64_pte_noexec_guard(cpu
, pte
);
809 pp_prot
= ppc_hash64_pte_prot(cpu
, slb
, pte
);
810 amr_prot
= ppc_hash64_amr_prot(cpu
, pte
);
811 prot
= exec_prot
& pp_prot
& amr_prot
;
813 if ((need_prot
[rwx
] & ~prot
) != 0) {
814 /* Access right violation */
815 qemu_log_mask(CPU_LOG_MMU
, "PTE access rejected\n");
818 if (PAGE_EXEC
& ~exec_prot
) {
819 srr1
|= SRR1_NOEXEC_GUARD
; /* Access violates noexec or guard */
820 } else if (PAGE_EXEC
& ~pp_prot
) {
821 srr1
|= SRR1_PROTFAULT
; /* Access violates access authority */
823 if (PAGE_EXEC
& ~amr_prot
) {
824 srr1
|= SRR1_IAMR
; /* Access violates virt pg class key prot */
826 ppc_hash64_set_isi(cs
, srr1
);
829 if (need_prot
[rwx
] & ~pp_prot
) {
830 dsisr
|= DSISR_PROTFAULT
;
833 dsisr
|= DSISR_ISSTORE
;
835 if (need_prot
[rwx
] & ~amr_prot
) {
838 ppc_hash64_set_dsi(cs
, eaddr
, dsisr
);
843 qemu_log_mask(CPU_LOG_MMU
, "PTE access granted !\n");
845 /* 6. Update PTE referenced and changed bits if necessary */
847 new_pte1
= pte
.pte1
| HPTE64_R_R
; /* set referenced bit */
849 new_pte1
|= HPTE64_R_C
; /* set changed (dirty) bit */
851 /* Treat the page as read-only for now, so that a later write
852 * will pass through this function again to set the C bit */
856 if (new_pte1
!= pte
.pte1
) {
857 ppc_hash64_store_hpte(cpu
, ptex
, pte
.pte0
, new_pte1
);
860 /* 7. Determine the real address from the PTE */
862 raddr
= deposit64(pte
.pte1
& HPTE64_R_RPN
, 0, apshift
, eaddr
);
864 tlb_set_page(cs
, eaddr
& TARGET_PAGE_MASK
, raddr
& TARGET_PAGE_MASK
,
865 prot
, mmu_idx
, 1ULL << apshift
);
870 hwaddr
ppc_hash64_get_phys_page_debug(PowerPCCPU
*cpu
, target_ulong addr
)
872 CPUPPCState
*env
= &cpu
->env
;
875 ppc_hash_pte64_t pte
;
878 /* Handle real mode */
880 /* In real mode the top 4 effective address bits are ignored */
881 raddr
= addr
& 0x0FFFFFFFFFFFFFFFULL
;
883 /* In HV mode, add HRMOR if top EA bit is clear */
884 if ((msr_hv
|| !env
->has_hv_mode
) && !(addr
>> 63)) {
885 return raddr
| env
->spr
[SPR_HRMOR
];
888 /* Otherwise, check VPM for RMA vs VRMA */
889 if (env
->spr
[SPR_LPCR
] & LPCR_VPM0
) {
890 slb
= &env
->vrma_slb
;
894 } else if (raddr
< env
->rmls
) {
895 /* RMA. Check bounds in RMLS */
896 return raddr
| env
->spr
[SPR_RMOR
];
901 slb
= slb_lookup(cpu
, addr
);
907 ptex
= ppc_hash64_htab_lookup(cpu
, slb
, addr
, &pte
, &apshift
);
912 return deposit64(pte
.pte1
& HPTE64_R_RPN
, 0, apshift
, addr
)
916 void ppc_hash64_store_hpte(PowerPCCPU
*cpu
, hwaddr ptex
,
917 uint64_t pte0
, uint64_t pte1
)
919 hwaddr base
= ppc_hash64_hpt_base(cpu
);
920 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
923 PPCVirtualHypervisorClass
*vhc
=
924 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
925 vhc
->store_hpte(cpu
->vhyp
, ptex
, pte0
, pte1
);
929 stq_phys(CPU(cpu
)->as
, base
+ offset
, pte0
);
930 stq_phys(CPU(cpu
)->as
, base
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
933 void ppc_hash64_tlb_flush_hpte(PowerPCCPU
*cpu
, target_ulong ptex
,
934 target_ulong pte0
, target_ulong pte1
)
937 * XXX: given the fact that there are too many segments to
938 * invalidate, and we still don't have a tlb_flush_mask(env, n,
939 * mask) in QEMU, we just invalidate all TLBs
941 cpu
->env
.tlb_need_flush
= TLB_NEED_GLOBAL_FLUSH
| TLB_NEED_LOCAL_FLUSH
;
944 void ppc_hash64_update_rmls(PowerPCCPU
*cpu
)
946 CPUPPCState
*env
= &cpu
->env
;
947 uint64_t lpcr
= env
->spr
[SPR_LPCR
];
950 * This is the full 4 bits encoding of POWER8. Previous
951 * CPUs only support a subset of these but the filtering
952 * is done when writing LPCR
954 switch ((lpcr
& LPCR_RMLS
) >> LPCR_RMLS_SHIFT
) {
956 env
->rmls
= 0x2000000ull
;
959 env
->rmls
= 0x4000000ull
;
961 case 0x7: /* 128MB */
962 env
->rmls
= 0x8000000ull
;
964 case 0x4: /* 256MB */
965 env
->rmls
= 0x10000000ull
;
968 env
->rmls
= 0x40000000ull
;
971 env
->rmls
= 0x400000000ull
;
974 /* What to do here ??? */
979 void ppc_hash64_update_vrma(PowerPCCPU
*cpu
)
981 CPUPPCState
*env
= &cpu
->env
;
982 const PPCHash64SegmentPageSizes
*sps
= NULL
;
983 target_ulong esid
, vsid
, lpcr
;
984 ppc_slb_t
*slb
= &env
->vrma_slb
;
989 slb
->esid
= slb
->vsid
= 0;
992 /* Is VRMA enabled ? */
993 lpcr
= env
->spr
[SPR_LPCR
];
994 if (!(lpcr
& LPCR_VPM0
)) {
998 /* Make one up. Mostly ignore the ESID which will not be
999 * needed for translation
1001 vsid
= SLB_VSID_VRMA
;
1002 vrmasd
= (lpcr
& LPCR_VRMASD
) >> LPCR_VRMASD_SHIFT
;
1003 vsid
|= (vrmasd
<< 4) & (SLB_VSID_L
| SLB_VSID_LP
);
1006 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
1007 const PPCHash64SegmentPageSizes
*sps1
= &cpu
->hash64_opts
->sps
[i
];
1009 if (!sps1
->page_shift
) {
1013 if ((vsid
& SLB_VSID_LLP_MASK
) == sps1
->slb_enc
) {
1020 error_report("Bad page size encoding esid 0x"TARGET_FMT_lx
1021 " vsid 0x"TARGET_FMT_lx
, esid
, vsid
);
1030 void helper_store_lpcr(CPUPPCState
*env
, target_ulong val
)
1032 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
1035 /* Filter out bits */
1036 switch (POWERPC_MMU_VER(env
->mmu_model
)) {
1037 case POWERPC_MMU_VER_64B
: /* 970 */
1041 if (val
& 0x8000000000000000ull
) {
1045 lpcr
|= (0x4ull
<< LPCR_RMLS_SHIFT
);
1047 if (val
& 0x4000000000000000ull
) {
1048 lpcr
|= (0x2ull
<< LPCR_RMLS_SHIFT
);
1050 if (val
& 0x2000000000000000ull
) {
1051 lpcr
|= (0x1ull
<< LPCR_RMLS_SHIFT
);
1053 env
->spr
[SPR_RMOR
] = ((lpcr
>> 41) & 0xffffull
) << 26;
1055 /* XXX We could also write LPID from HID4 here
1056 * but since we don't tag any translation on it
1057 * it doesn't actually matter
1059 /* XXX For proper emulation of 970 we also need
1060 * to dig HRMOR out of HID5
1063 case POWERPC_MMU_VER_2_03
: /* P5p */
1064 lpcr
= val
& (LPCR_RMLS
| LPCR_ILE
|
1065 LPCR_LPES0
| LPCR_LPES1
|
1066 LPCR_RMI
| LPCR_HDICE
);
1068 case POWERPC_MMU_VER_2_06
: /* P7 */
1069 lpcr
= val
& (LPCR_VPM0
| LPCR_VPM1
| LPCR_ISL
| LPCR_DPFD
|
1070 LPCR_VRMASD
| LPCR_RMLS
| LPCR_ILE
|
1071 LPCR_P7_PECE0
| LPCR_P7_PECE1
| LPCR_P7_PECE2
|
1072 LPCR_MER
| LPCR_TC
|
1073 LPCR_LPES0
| LPCR_LPES1
| LPCR_HDICE
);
1075 case POWERPC_MMU_VER_2_07
: /* P8 */
1076 lpcr
= val
& (LPCR_VPM0
| LPCR_VPM1
| LPCR_ISL
| LPCR_KBV
|
1077 LPCR_DPFD
| LPCR_VRMASD
| LPCR_RMLS
| LPCR_ILE
|
1078 LPCR_AIL
| LPCR_ONL
| LPCR_P8_PECE0
| LPCR_P8_PECE1
|
1079 LPCR_P8_PECE2
| LPCR_P8_PECE3
| LPCR_P8_PECE4
|
1080 LPCR_MER
| LPCR_TC
| LPCR_LPES0
| LPCR_HDICE
);
1082 case POWERPC_MMU_VER_3_00
: /* P9 */
1083 lpcr
= val
& (LPCR_VPM1
| LPCR_ISL
| LPCR_KBV
| LPCR_DPFD
|
1084 (LPCR_PECE_U_MASK
& LPCR_HVEE
) | LPCR_ILE
| LPCR_AIL
|
1085 LPCR_UPRT
| LPCR_EVIRT
| LPCR_ONL
|
1086 (LPCR_PECE_L_MASK
& (LPCR_PDEE
| LPCR_HDEE
| LPCR_EEE
|
1087 LPCR_DEE
| LPCR_OEE
)) | LPCR_MER
| LPCR_GTSE
| LPCR_TC
|
1088 LPCR_HEIC
| LPCR_LPES0
| LPCR_HVICE
| LPCR_HDICE
);
1093 env
->spr
[SPR_LPCR
] = lpcr
;
1094 ppc_hash64_update_rmls(cpu
);
1095 ppc_hash64_update_vrma(cpu
);
1098 void ppc_hash64_init(PowerPCCPU
*cpu
)
1100 CPUPPCState
*env
= &cpu
->env
;
1101 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
1103 if (pcc
->hash64_opts
) {
1104 cpu
->hash64_opts
= g_memdup(pcc
->hash64_opts
,
1105 sizeof(*cpu
->hash64_opts
));
1106 } else if (env
->mmu_model
& POWERPC_MMU_64
) {
1107 /* Use default sets of page sizes. We don't support MPSS */
1108 static const PPCHash64Options defopts
= {
1110 { .page_shift
= 12, /* 4K */
1112 .enc
= { { .page_shift
= 12, .pte_enc
= 0 } }
1114 { .page_shift
= 24, /* 16M */
1116 .enc
= { { .page_shift
= 24, .pte_enc
= 0 } }
1120 cpu
->hash64_opts
= g_memdup(&defopts
, sizeof(*cpu
->hash64_opts
));
1124 void ppc_hash64_finalize(PowerPCCPU
*cpu
)
1126 g_free(cpu
->hash64_opts
);
1129 const PPCHash64Options ppc_hash64_opts_POWER7
= {
1132 .page_shift
= 12, /* 4K */
1134 .enc
= { { .page_shift
= 12, .pte_enc
= 0 },
1135 { .page_shift
= 16, .pte_enc
= 0x7 },
1136 { .page_shift
= 24, .pte_enc
= 0x38 }, },
1139 .page_shift
= 16, /* 64K */
1140 .slb_enc
= SLB_VSID_64K
,
1141 .enc
= { { .page_shift
= 16, .pte_enc
= 0x1 },
1142 { .page_shift
= 24, .pte_enc
= 0x8 }, },
1145 .page_shift
= 24, /* 16M */
1146 .slb_enc
= SLB_VSID_16M
,
1147 .enc
= { { .page_shift
= 24, .pte_enc
= 0 }, },
1150 .page_shift
= 34, /* 16G */
1151 .slb_enc
= SLB_VSID_16G
,
1152 .enc
= { { .page_shift
= 34, .pte_enc
= 0x3 }, },