2 * Xilinx Zynq Baseboard System emulation.
4 * Copyright (c) 2010 Xilinx.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
6 * Copyright (c) 2012 Petalogix Pty Ltd.
7 * Written by Haibing Ma
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 #include "qemu/osdep.h"
19 #include "qapi/error.h"
20 #include "qemu-common.h"
22 #include "hw/sysbus.h"
23 #include "hw/arm/arm.h"
25 #include "exec/address-spaces.h"
26 #include "sysemu/sysemu.h"
27 #include "hw/boards.h"
28 #include "hw/block/flash.h"
29 #include "sysemu/block-backend.h"
30 #include "hw/loader.h"
31 #include "hw/misc/zynq-xadc.h"
32 #include "hw/ssi/ssi.h"
33 #include "qemu/error-report.h"
35 #include "hw/char/cadence_uart.h"
37 #define NUM_SPI_FLASHES 4
38 #define NUM_QSPI_FLASHES 2
39 #define NUM_QSPI_BUSSES 2
41 #define FLASH_SIZE (64 * 1024 * 1024)
42 #define FLASH_SECTOR_SIZE (128 * 1024)
44 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
46 #define MPCORE_PERIPHBASE 0xF8F00000
47 #define ZYNQ_BOARD_MIDR 0x413FC090
49 static const int dma_irqs
[8] = {
50 46, 47, 48, 49, 72, 73, 74, 75
53 #define BOARD_SETUP_ADDR 0x100
55 #define SLCR_LOCK_OFFSET 0x004
56 #define SLCR_UNLOCK_OFFSET 0x008
57 #define SLCR_ARM_PLL_OFFSET 0x100
59 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
60 #define SLCR_XILINX_LOCK_KEY 0x767b
62 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
63 extract32((x), 12, 4) << 16)
65 /* Write immediate val to address r0 + addr. r0 should contain base offset
66 * of the SLCR block. Clobbers r1.
69 #define SLCR_WRITE(addr, val) \
70 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
71 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
74 static void zynq_write_board_setup(ARMCPU
*cpu
,
75 const struct arm_boot_info
*info
)
78 uint32_t board_setup_blob
[] = {
79 0xe3a004f8, /* mov r0, #0xf8000000 */
80 SLCR_WRITE(SLCR_UNLOCK_OFFSET
, SLCR_XILINX_UNLOCK_KEY
),
81 SLCR_WRITE(SLCR_ARM_PLL_OFFSET
, 0x00014008),
82 SLCR_WRITE(SLCR_LOCK_OFFSET
, SLCR_XILINX_LOCK_KEY
),
83 0xe12fff1e, /* bx lr */
85 for (n
= 0; n
< ARRAY_SIZE(board_setup_blob
); n
++) {
86 board_setup_blob
[n
] = tswap32(board_setup_blob
[n
]);
88 rom_add_blob_fixed("board-setup", board_setup_blob
,
89 sizeof(board_setup_blob
), BOARD_SETUP_ADDR
);
92 static struct arm_boot_info zynq_binfo
= {};
94 static void gem_init(NICInfo
*nd
, uint32_t base
, qemu_irq irq
)
99 dev
= qdev_create(NULL
, "cadence_gem");
101 qemu_check_nic_model(nd
, "cadence_gem");
102 qdev_set_nic_properties(dev
, nd
);
104 qdev_init_nofail(dev
);
105 s
= SYS_BUS_DEVICE(dev
);
106 sysbus_mmio_map(s
, 0, base
);
107 sysbus_connect_irq(s
, 0, irq
);
110 static inline void zynq_init_spi_flashes(uint32_t base_addr
, qemu_irq irq
,
114 SysBusDevice
*busdev
;
116 DeviceState
*flash_dev
;
118 int num_busses
= is_qspi
? NUM_QSPI_BUSSES
: 1;
119 int num_ss
= is_qspi
? NUM_QSPI_FLASHES
: NUM_SPI_FLASHES
;
121 dev
= qdev_create(NULL
, is_qspi
? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
122 qdev_prop_set_uint8(dev
, "num-txrx-bytes", is_qspi
? 4 : 1);
123 qdev_prop_set_uint8(dev
, "num-ss-bits", num_ss
);
124 qdev_prop_set_uint8(dev
, "num-busses", num_busses
);
125 qdev_init_nofail(dev
);
126 busdev
= SYS_BUS_DEVICE(dev
);
127 sysbus_mmio_map(busdev
, 0, base_addr
);
129 sysbus_mmio_map(busdev
, 1, 0xFC000000);
131 sysbus_connect_irq(busdev
, 0, irq
);
133 for (i
= 0; i
< num_busses
; ++i
) {
137 snprintf(bus_name
, 16, "spi%d", i
);
138 spi
= (SSIBus
*)qdev_get_child_bus(dev
, bus_name
);
140 for (j
= 0; j
< num_ss
; ++j
) {
141 DriveInfo
*dinfo
= drive_get_next(IF_MTD
);
142 flash_dev
= ssi_create_slave_no_init(spi
, "n25q128");
144 qdev_prop_set_drive(flash_dev
, "drive",
145 blk_by_legacy_dinfo(dinfo
), &error_fatal
);
147 qdev_init_nofail(flash_dev
);
149 cs_line
= qdev_get_gpio_in_named(flash_dev
, SSI_GPIO_CS
, 0);
150 sysbus_connect_irq(busdev
, i
* num_ss
+ j
+ 1, cs_line
);
156 static void zynq_init(MachineState
*machine
)
158 ram_addr_t ram_size
= machine
->ram_size
;
159 const char *cpu_model
= machine
->cpu_model
;
160 const char *kernel_filename
= machine
->kernel_filename
;
161 const char *kernel_cmdline
= machine
->kernel_cmdline
;
162 const char *initrd_filename
= machine
->initrd_filename
;
165 MemoryRegion
*address_space_mem
= get_system_memory();
166 MemoryRegion
*ext_ram
= g_new(MemoryRegion
, 1);
167 MemoryRegion
*ocm_ram
= g_new(MemoryRegion
, 1);
168 DeviceState
*dev
, *carddev
;
169 SysBusDevice
*busdev
;
176 cpu_model
= "cortex-a9";
178 cpu_oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpu_model
);
180 cpu
= ARM_CPU(object_new(object_class_get_name(cpu_oc
)));
182 /* By default A9 CPUs have EL3 enabled. This board does not
183 * currently support EL3 so the CPU EL3 property is disabled before
186 if (object_property_find(OBJECT(cpu
), "has_el3", NULL
)) {
187 object_property_set_bool(OBJECT(cpu
), false, "has_el3", &error_fatal
);
190 object_property_set_int(OBJECT(cpu
), ZYNQ_BOARD_MIDR
, "midr",
192 object_property_set_int(OBJECT(cpu
), MPCORE_PERIPHBASE
, "reset-cbar",
194 object_property_set_bool(OBJECT(cpu
), true, "realized", &error_fatal
);
197 if (ram_size
> 0x80000000) {
198 ram_size
= 0x80000000;
201 /* DDR remapped to address zero. */
202 memory_region_allocate_system_memory(ext_ram
, NULL
, "zynq.ext_ram",
204 memory_region_add_subregion(address_space_mem
, 0, ext_ram
);
206 /* 256K of on-chip memory */
207 memory_region_init_ram(ocm_ram
, NULL
, "zynq.ocm_ram", 256 << 10,
209 memory_region_add_subregion(address_space_mem
, 0xFFFC0000, ocm_ram
);
211 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
214 pflash_cfi02_register(0xe2000000, NULL
, "zynq.pflash", FLASH_SIZE
,
215 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
217 FLASH_SIZE
/FLASH_SECTOR_SIZE
, 1,
218 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
221 dev
= qdev_create(NULL
, "xilinx,zynq_slcr");
222 qdev_init_nofail(dev
);
223 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xF8000000);
225 dev
= qdev_create(NULL
, "a9mpcore_priv");
226 qdev_prop_set_uint32(dev
, "num-cpu", 1);
227 qdev_init_nofail(dev
);
228 busdev
= SYS_BUS_DEVICE(dev
);
229 sysbus_mmio_map(busdev
, 0, MPCORE_PERIPHBASE
);
230 sysbus_connect_irq(busdev
, 0,
231 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
));
233 for (n
= 0; n
< 64; n
++) {
234 pic
[n
] = qdev_get_gpio_in(dev
, n
);
237 zynq_init_spi_flashes(0xE0006000, pic
[58-IRQ_OFFSET
], false);
238 zynq_init_spi_flashes(0xE0007000, pic
[81-IRQ_OFFSET
], false);
239 zynq_init_spi_flashes(0xE000D000, pic
[51-IRQ_OFFSET
], true);
241 sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic
[53-IRQ_OFFSET
]);
242 sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic
[76-IRQ_OFFSET
]);
244 cadence_uart_create(0xE0000000, pic
[59 - IRQ_OFFSET
], serial_hds
[0]);
245 cadence_uart_create(0xE0001000, pic
[82 - IRQ_OFFSET
], serial_hds
[1]);
247 sysbus_create_varargs("cadence_ttc", 0xF8001000,
248 pic
[42-IRQ_OFFSET
], pic
[43-IRQ_OFFSET
], pic
[44-IRQ_OFFSET
], NULL
);
249 sysbus_create_varargs("cadence_ttc", 0xF8002000,
250 pic
[69-IRQ_OFFSET
], pic
[70-IRQ_OFFSET
], pic
[71-IRQ_OFFSET
], NULL
);
252 gem_init(&nd_table
[0], 0xE000B000, pic
[54-IRQ_OFFSET
]);
253 gem_init(&nd_table
[1], 0xE000C000, pic
[77-IRQ_OFFSET
]);
255 dev
= qdev_create(NULL
, "generic-sdhci");
256 qdev_init_nofail(dev
);
257 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xE0100000);
258 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[56-IRQ_OFFSET
]);
260 di
= drive_get_next(IF_SD
);
261 blk
= di
? blk_by_legacy_dinfo(di
) : NULL
;
262 carddev
= qdev_create(qdev_get_child_bus(dev
, "sd-bus"), TYPE_SD_CARD
);
263 qdev_prop_set_drive(carddev
, "drive", blk
, &error_fatal
);
264 object_property_set_bool(OBJECT(carddev
), true, "realized", &error_fatal
);
266 dev
= qdev_create(NULL
, "generic-sdhci");
267 qdev_init_nofail(dev
);
268 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xE0101000);
269 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[79-IRQ_OFFSET
]);
271 di
= drive_get_next(IF_SD
);
272 blk
= di
? blk_by_legacy_dinfo(di
) : NULL
;
273 carddev
= qdev_create(qdev_get_child_bus(dev
, "sd-bus"), TYPE_SD_CARD
);
274 qdev_prop_set_drive(carddev
, "drive", blk
, &error_fatal
);
275 object_property_set_bool(OBJECT(carddev
), true, "realized", &error_fatal
);
277 dev
= qdev_create(NULL
, TYPE_ZYNQ_XADC
);
278 qdev_init_nofail(dev
);
279 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, 0xF8007100);
280 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[39-IRQ_OFFSET
]);
282 dev
= qdev_create(NULL
, "pl330");
283 qdev_prop_set_uint8(dev
, "num_chnls", 8);
284 qdev_prop_set_uint8(dev
, "num_periph_req", 4);
285 qdev_prop_set_uint8(dev
, "num_events", 16);
287 qdev_prop_set_uint8(dev
, "data_width", 64);
288 qdev_prop_set_uint8(dev
, "wr_cap", 8);
289 qdev_prop_set_uint8(dev
, "wr_q_dep", 16);
290 qdev_prop_set_uint8(dev
, "rd_cap", 8);
291 qdev_prop_set_uint8(dev
, "rd_q_dep", 16);
292 qdev_prop_set_uint16(dev
, "data_buffer_dep", 256);
294 qdev_init_nofail(dev
);
295 busdev
= SYS_BUS_DEVICE(dev
);
296 sysbus_mmio_map(busdev
, 0, 0xF8003000);
297 sysbus_connect_irq(busdev
, 0, pic
[45-IRQ_OFFSET
]); /* abort irq line */
298 for (n
= 0; n
< 8; ++n
) { /* event irqs */
299 sysbus_connect_irq(busdev
, n
+ 1, pic
[dma_irqs
[n
] - IRQ_OFFSET
]);
302 dev
= qdev_create(NULL
, "xlnx.ps7-dev-cfg");
303 qdev_init_nofail(dev
);
304 busdev
= SYS_BUS_DEVICE(dev
);
305 sysbus_connect_irq(busdev
, 0, pic
[40 - IRQ_OFFSET
]);
306 sysbus_mmio_map(busdev
, 0, 0xF8007000);
308 zynq_binfo
.ram_size
= ram_size
;
309 zynq_binfo
.kernel_filename
= kernel_filename
;
310 zynq_binfo
.kernel_cmdline
= kernel_cmdline
;
311 zynq_binfo
.initrd_filename
= initrd_filename
;
312 zynq_binfo
.nb_cpus
= 1;
313 zynq_binfo
.board_id
= 0xd32;
314 zynq_binfo
.loader_start
= 0;
315 zynq_binfo
.board_setup_addr
= BOARD_SETUP_ADDR
;
316 zynq_binfo
.write_board_setup
= zynq_write_board_setup
;
318 arm_load_kernel(ARM_CPU(first_cpu
), &zynq_binfo
);
321 static void zynq_machine_init(MachineClass
*mc
)
323 mc
->desc
= "Xilinx Zynq Platform Baseboard for Cortex-A9";
324 mc
->init
= zynq_init
;
329 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init
)