2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
33 #include "hw/fw-path-provider.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
41 #include "migration/migration.h"
42 #include "mmu-hash64.h"
43 #include "mmu-book3s-v3.h"
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
50 #include "hw/ppc/fdt.h"
51 #include "hw/ppc/spapr.h"
52 #include "hw/ppc/spapr_vio.h"
53 #include "hw/pci-host/spapr.h"
54 #include "hw/ppc/xics.h"
55 #include "hw/pci/msi.h"
57 #include "hw/pci/pci.h"
58 #include "hw/scsi/scsi.h"
59 #include "hw/virtio/virtio-scsi.h"
61 #include "exec/address-spaces.h"
63 #include "qemu/config-file.h"
64 #include "qemu/error-report.h"
67 #include "hw/intc/intc.h"
69 #include "hw/compat.h"
70 #include "qemu/cutils.h"
71 #include "hw/ppc/spapr_cpu_core.h"
72 #include "qmp-commands.h"
76 /* SLOF memory layout:
78 * SLOF raw image loaded at 0, copies its romfs right below the flat
79 * device-tree, then position SLOF itself 31M below that
81 * So we set FW_OVERHEAD to 40MB which should account for all of that
84 * We load our kernel at 4M, leaving space for SLOF initial image
86 #define FDT_MAX_SIZE 0x100000
87 #define RTAS_MAX_SIZE 0x10000
88 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
89 #define FW_MAX_SIZE 0x400000
90 #define FW_FILE_NAME "slof.bin"
91 #define FW_OVERHEAD 0x2800000
92 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
94 #define MIN_RMA_SLOF 128UL
96 #define PHANDLE_XICP 0x00001111
98 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
100 static ICSState
*spapr_ics_create(sPAPRMachineState
*spapr
,
101 const char *type_ics
,
102 int nr_irqs
, Error
**errp
)
104 Error
*err
= NULL
, *local_err
= NULL
;
107 obj
= object_new(type_ics
);
108 object_property_add_child(OBJECT(spapr
), "ics", obj
, NULL
);
109 object_property_add_const_link(obj
, "xics", OBJECT(spapr
), &error_abort
);
110 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &err
);
111 object_property_set_bool(obj
, true, "realized", &local_err
);
112 error_propagate(&err
, local_err
);
114 error_propagate(errp
, err
);
118 return ICS_SIMPLE(obj
);
121 static void xics_system_init(MachineState
*machine
, int nr_irqs
, Error
**errp
)
123 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
128 if (machine_kernel_irqchip_allowed(machine
) &&
129 !xics_kvm_init(spapr
, errp
)) {
130 spapr
->icp_type
= TYPE_KVM_ICP
;
131 spapr
->ics
= spapr_ics_create(spapr
, TYPE_ICS_KVM
, nr_irqs
, &err
);
133 if (machine_kernel_irqchip_required(machine
) && !spapr
->ics
) {
134 error_reportf_err(err
,
135 "kernel_irqchip requested but unavailable: ");
142 xics_spapr_init(spapr
, errp
);
143 spapr
->icp_type
= TYPE_ICP
;
144 spapr
->ics
= spapr_ics_create(spapr
, TYPE_ICS_SIMPLE
, nr_irqs
, errp
);
148 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
152 uint32_t servers_prop
[smt_threads
];
153 uint32_t gservers_prop
[smt_threads
* 2];
154 int index
= ppc_get_vcpu_dt_id(cpu
);
156 if (cpu
->compat_pvr
) {
157 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
163 /* Build interrupt servers and gservers properties */
164 for (i
= 0; i
< smt_threads
; i
++) {
165 servers_prop
[i
] = cpu_to_be32(index
+ i
);
166 /* Hack, direct the group queues back to cpu 0 */
167 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
168 gservers_prop
[i
*2 + 1] = 0;
170 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
171 servers_prop
, sizeof(servers_prop
));
175 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
176 gservers_prop
, sizeof(gservers_prop
));
181 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, CPUState
*cs
)
184 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
185 int index
= ppc_get_vcpu_dt_id(cpu
);
186 uint32_t associativity
[] = {cpu_to_be32(0x5),
190 cpu_to_be32(cs
->numa_node
),
193 /* Advertise NUMA via ibm,associativity */
194 if (nb_numa_nodes
> 1) {
195 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
196 sizeof(associativity
));
202 /* Populate the "ibm,pa-features" property */
203 static void spapr_populate_pa_features(CPUPPCState
*env
, void *fdt
, int offset
,
206 uint8_t pa_features_206
[] = { 6, 0,
207 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
208 uint8_t pa_features_207
[] = { 24, 0,
209 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
210 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
211 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
212 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
213 uint8_t pa_features_300
[] = { 66, 0,
214 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
215 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
218 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
220 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
221 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
222 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
223 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
224 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
225 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
226 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
227 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
229 /* 42: PM, 44: PC RA, 46: SC vec'd */
230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
231 /* 48: SIMD, 50: QP BFP, 52: String */
232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
233 /* 54: DecFP, 56: DecI, 58: SHA */
234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
235 /* 60: NM atomic, 62: RNG */
236 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
238 uint8_t *pa_features
;
241 switch (POWERPC_MMU_VER(env
->mmu_model
)) {
242 case POWERPC_MMU_VER_2_06
:
243 pa_features
= pa_features_206
;
244 pa_size
= sizeof(pa_features_206
);
246 case POWERPC_MMU_VER_2_07
:
247 pa_features
= pa_features_207
;
248 pa_size
= sizeof(pa_features_207
);
250 case POWERPC_MMU_VER_3_00
:
251 pa_features
= pa_features_300
;
252 pa_size
= sizeof(pa_features_300
);
258 if (env
->ci_large_pages
) {
260 * Note: we keep CI large pages off by default because a 64K capable
261 * guest provisioned with large pages might otherwise try to map a qemu
262 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
263 * even if that qemu runs on a 4k host.
264 * We dd this bit back here if we are confident this is not an issue
266 pa_features
[3] |= 0x20;
268 if (kvmppc_has_cap_htm() && pa_size
> 24) {
269 pa_features
[24] |= 0x80; /* Transactional memory support */
271 if (legacy_guest
&& pa_size
> 40) {
272 /* Workaround for broken kernels that attempt (guest) radix
273 * mode when they can't handle it, if they see the radix bit set
274 * in pa-features. So hide it from them. */
275 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
278 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
281 static int spapr_fixup_cpu_dt(void *fdt
, sPAPRMachineState
*spapr
)
283 int ret
= 0, offset
, cpus_offset
;
286 int smt
= kvmppc_smt_threads();
287 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
290 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
291 CPUPPCState
*env
= &cpu
->env
;
292 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
293 int index
= ppc_get_vcpu_dt_id(cpu
);
294 int compat_smt
= MIN(smp_threads
, ppc_compat_max_threads(cpu
));
296 if ((index
% smt
) != 0) {
300 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
302 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
303 if (cpus_offset
< 0) {
304 cpus_offset
= fdt_add_subnode(fdt
, fdt_path_offset(fdt
, "/"),
306 if (cpus_offset
< 0) {
310 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
312 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
318 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
319 pft_size_prop
, sizeof(pft_size_prop
));
324 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cs
);
329 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
);
334 spapr_populate_pa_features(env
, fdt
, offset
,
335 spapr
->cas_legacy_guest_workaround
);
340 static hwaddr
spapr_node0_size(void)
342 MachineState
*machine
= MACHINE(qdev_get_machine());
346 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
347 if (numa_info
[i
].node_mem
) {
348 return MIN(pow2floor(numa_info
[i
].node_mem
),
353 return machine
->ram_size
;
356 static void add_str(GString
*s
, const gchar
*s1
)
358 g_string_append_len(s
, s1
, strlen(s1
) + 1);
361 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
364 uint32_t associativity
[] = {
365 cpu_to_be32(0x4), /* length */
366 cpu_to_be32(0x0), cpu_to_be32(0x0),
367 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
370 uint64_t mem_reg_property
[2];
373 mem_reg_property
[0] = cpu_to_be64(start
);
374 mem_reg_property
[1] = cpu_to_be64(size
);
376 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
377 off
= fdt_add_subnode(fdt
, 0, mem_name
);
379 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
380 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
381 sizeof(mem_reg_property
))));
382 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
383 sizeof(associativity
))));
387 static int spapr_populate_memory(sPAPRMachineState
*spapr
, void *fdt
)
389 MachineState
*machine
= MACHINE(spapr
);
390 hwaddr mem_start
, node_size
;
391 int i
, nb_nodes
= nb_numa_nodes
;
392 NodeInfo
*nodes
= numa_info
;
395 /* No NUMA nodes, assume there is just one node with whole RAM */
396 if (!nb_numa_nodes
) {
398 ramnode
.node_mem
= machine
->ram_size
;
402 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
403 if (!nodes
[i
].node_mem
) {
406 if (mem_start
>= machine
->ram_size
) {
409 node_size
= nodes
[i
].node_mem
;
410 if (node_size
> machine
->ram_size
- mem_start
) {
411 node_size
= machine
->ram_size
- mem_start
;
415 /* ppc_spapr_init() checks for rma_size <= node0_size already */
416 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
417 mem_start
+= spapr
->rma_size
;
418 node_size
-= spapr
->rma_size
;
420 for ( ; node_size
; ) {
421 hwaddr sizetmp
= pow2floor(node_size
);
423 /* mem_start != 0 here */
424 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
425 sizetmp
= 1ULL << ctzl(mem_start
);
428 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
429 node_size
-= sizetmp
;
430 mem_start
+= sizetmp
;
437 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
438 sPAPRMachineState
*spapr
)
440 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
441 CPUPPCState
*env
= &cpu
->env
;
442 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
443 int index
= ppc_get_vcpu_dt_id(cpu
);
444 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
445 0xffffffff, 0xffffffff};
446 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
447 : SPAPR_TIMEBASE_FREQ
;
448 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
449 uint32_t page_sizes_prop
[64];
450 size_t page_sizes_prop_size
;
451 uint32_t vcpus_per_socket
= smp_threads
* smp_cores
;
452 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
453 int compat_smt
= MIN(smp_threads
, ppc_compat_max_threads(cpu
));
454 sPAPRDRConnector
*drc
;
455 sPAPRDRConnectorClass
*drck
;
457 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
460 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU
, index
);
462 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
463 drc_index
= drck
->get_index(drc
);
464 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
467 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
468 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
470 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
471 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
472 env
->dcache_line_size
)));
473 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
474 env
->dcache_line_size
)));
475 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
476 env
->icache_line_size
)));
477 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
478 env
->icache_line_size
)));
480 if (pcc
->l1_dcache_size
) {
481 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
482 pcc
->l1_dcache_size
)));
484 error_report("Warning: Unknown L1 dcache size for cpu");
486 if (pcc
->l1_icache_size
) {
487 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
488 pcc
->l1_icache_size
)));
490 error_report("Warning: Unknown L1 icache size for cpu");
493 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
494 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
495 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", env
->slb_nr
)));
496 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", env
->slb_nr
)));
497 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
498 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
500 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
501 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
504 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
505 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
506 segs
, sizeof(segs
))));
509 /* Advertise VMX/VSX (vector extensions) if available
510 * 0 / no property == no vector extensions
511 * 1 == VMX / Altivec available
512 * 2 == VSX available */
513 if (env
->insns_flags
& PPC_ALTIVEC
) {
514 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
516 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
519 /* Advertise DFP (Decimal Floating Point) if available
520 * 0 / no property == no DFP
521 * 1 == DFP available */
522 if (env
->insns_flags2
& PPC2_DFP
) {
523 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
526 page_sizes_prop_size
= ppc_create_page_sizes_prop(env
, page_sizes_prop
,
527 sizeof(page_sizes_prop
));
528 if (page_sizes_prop_size
) {
529 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
530 page_sizes_prop
, page_sizes_prop_size
)));
533 spapr_populate_pa_features(env
, fdt
, offset
, false);
535 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
536 cs
->cpu_index
/ vcpus_per_socket
)));
538 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
539 pft_size_prop
, sizeof(pft_size_prop
))));
541 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cs
));
543 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
545 if (pcc
->radix_page_info
) {
546 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
547 radix_AP_encodings
[i
] =
548 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
550 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
552 pcc
->radix_page_info
->count
*
553 sizeof(radix_AP_encodings
[0]))));
557 static void spapr_populate_cpus_dt_node(void *fdt
, sPAPRMachineState
*spapr
)
562 int smt
= kvmppc_smt_threads();
564 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
566 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
567 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
570 * We walk the CPUs in reverse order to ensure that CPU DT nodes
571 * created by fdt_add_subnode() end up in the right order in FDT
572 * for the guest kernel the enumerate the CPUs correctly.
574 CPU_FOREACH_REVERSE(cs
) {
575 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
576 int index
= ppc_get_vcpu_dt_id(cpu
);
577 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
580 if ((index
% smt
) != 0) {
584 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
585 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
588 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
594 * Adds ibm,dynamic-reconfiguration-memory node.
595 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
596 * of this device tree node.
598 static int spapr_populate_drconf_memory(sPAPRMachineState
*spapr
, void *fdt
)
600 MachineState
*machine
= MACHINE(spapr
);
602 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
603 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
604 uint32_t hotplug_lmb_start
= spapr
->hotplug_memory
.base
/ lmb_size
;
605 uint32_t nr_lmbs
= (spapr
->hotplug_memory
.base
+
606 memory_region_size(&spapr
->hotplug_memory
.mr
)) /
608 uint32_t *int_buf
, *cur_index
, buf_len
;
609 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
612 * Don't create the node if there is no hotpluggable memory
614 if (machine
->ram_size
== machine
->maxram_size
) {
619 * Allocate enough buffer size to fit in ibm,dynamic-memory
620 * or ibm,associativity-lookup-arrays
622 buf_len
= MAX(nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1, nr_nodes
* 4 + 2)
624 cur_index
= int_buf
= g_malloc0(buf_len
);
626 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
628 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
629 sizeof(prop_lmb_size
));
634 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
639 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
644 /* ibm,dynamic-memory */
645 int_buf
[0] = cpu_to_be32(nr_lmbs
);
647 for (i
= 0; i
< nr_lmbs
; i
++) {
648 uint64_t addr
= i
* lmb_size
;
649 uint32_t *dynamic_memory
= cur_index
;
651 if (i
>= hotplug_lmb_start
) {
652 sPAPRDRConnector
*drc
;
653 sPAPRDRConnectorClass
*drck
;
655 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
, i
);
657 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
659 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
660 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
661 dynamic_memory
[2] = cpu_to_be32(drck
->get_index(drc
));
662 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
663 dynamic_memory
[4] = cpu_to_be32(numa_get_node(addr
, NULL
));
664 if (memory_region_present(get_system_memory(), addr
)) {
665 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
667 dynamic_memory
[5] = cpu_to_be32(0);
671 * LMB information for RMA, boot time RAM and gap b/n RAM and
672 * hotplug memory region -- all these are marked as reserved
673 * and as having no valid DRC.
675 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
676 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
677 dynamic_memory
[2] = cpu_to_be32(0);
678 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
679 dynamic_memory
[4] = cpu_to_be32(-1);
680 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
681 SPAPR_LMB_FLAGS_DRC_INVALID
);
684 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
686 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
691 /* ibm,associativity-lookup-arrays */
693 int_buf
[0] = cpu_to_be32(nr_nodes
);
694 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
696 for (i
= 0; i
< nr_nodes
; i
++) {
697 uint32_t associativity
[] = {
703 memcpy(cur_index
, associativity
, sizeof(associativity
));
706 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
707 (cur_index
- int_buf
) * sizeof(uint32_t));
713 static int spapr_dt_cas_updates(sPAPRMachineState
*spapr
, void *fdt
,
714 sPAPROptionVector
*ov5_updates
)
716 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
719 /* Generate ibm,dynamic-reconfiguration-memory node if required */
720 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
721 g_assert(smc
->dr_lmb_enabled
);
722 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
728 offset
= fdt_path_offset(fdt
, "/chosen");
730 offset
= fdt_add_subnode(fdt
, 0, "chosen");
735 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
736 "ibm,architecture-vec-5");
742 int spapr_h_cas_compose_response(sPAPRMachineState
*spapr
,
743 target_ulong addr
, target_ulong size
,
744 sPAPROptionVector
*ov5_updates
)
746 void *fdt
, *fdt_skel
;
747 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
751 /* Create sceleton */
752 fdt_skel
= g_malloc0(size
);
753 _FDT((fdt_create(fdt_skel
, size
)));
754 _FDT((fdt_begin_node(fdt_skel
, "")));
755 _FDT((fdt_end_node(fdt_skel
)));
756 _FDT((fdt_finish(fdt_skel
)));
757 fdt
= g_malloc0(size
);
758 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
761 /* Fixup cpu nodes */
762 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
764 if (spapr_dt_cas_updates(spapr
, fdt
, ov5_updates
)) {
768 /* Pack resulting tree */
769 _FDT((fdt_pack(fdt
)));
771 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
772 trace_spapr_cas_failed(size
);
776 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
777 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
778 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
784 static void spapr_dt_rtas(sPAPRMachineState
*spapr
, void *fdt
)
787 GString
*hypertas
= g_string_sized_new(256);
788 GString
*qemu_hypertas
= g_string_sized_new(256);
789 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
790 uint64_t max_hotplug_addr
= spapr
->hotplug_memory
.base
+
791 memory_region_size(&spapr
->hotplug_memory
.mr
);
792 uint32_t lrdr_capacity
[] = {
793 cpu_to_be32(max_hotplug_addr
>> 32),
794 cpu_to_be32(max_hotplug_addr
& 0xffffffff),
795 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
796 cpu_to_be32(max_cpus
/ smp_threads
),
799 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
802 add_str(hypertas
, "hcall-pft");
803 add_str(hypertas
, "hcall-term");
804 add_str(hypertas
, "hcall-dabr");
805 add_str(hypertas
, "hcall-interrupt");
806 add_str(hypertas
, "hcall-tce");
807 add_str(hypertas
, "hcall-vio");
808 add_str(hypertas
, "hcall-splpar");
809 add_str(hypertas
, "hcall-bulk");
810 add_str(hypertas
, "hcall-set-mode");
811 add_str(hypertas
, "hcall-sprg0");
812 add_str(hypertas
, "hcall-copy");
813 add_str(hypertas
, "hcall-debug");
814 add_str(qemu_hypertas
, "hcall-memop1");
816 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
817 add_str(hypertas
, "hcall-multi-tce");
819 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
820 hypertas
->str
, hypertas
->len
));
821 g_string_free(hypertas
, TRUE
);
822 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
823 qemu_hypertas
->str
, qemu_hypertas
->len
));
824 g_string_free(qemu_hypertas
, TRUE
);
826 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
827 refpoints
, sizeof(refpoints
)));
829 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
830 RTAS_ERROR_LOG_MAX
));
831 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
832 RTAS_EVENT_SCAN_RATE
));
835 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
839 * According to PAPR, rtas ibm,os-term does not guarantee a return
840 * back to the guest cpu.
842 * While an additional ibm,extended-os-term property indicates
843 * that rtas call return will always occur. Set this property.
845 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
847 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
848 lrdr_capacity
, sizeof(lrdr_capacity
)));
850 spapr_dt_rtas_tokens(fdt
, rtas
);
853 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
854 * that the guest may request and thus the valid values for bytes 24..26 of
855 * option vector 5: */
856 static void spapr_dt_ov5_platform_support(void *fdt
, int chosen
)
859 24, 0x00, /* Hash/Radix, filled in below. */
860 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
861 26, 0x40, /* Radix options: GTSE == yes. */
865 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
866 val
[1] = 0x80; /* OV5_MMU_BOTH */
867 } else if (kvmppc_has_cap_mmu_radix()) {
868 val
[1] = 0x40; /* OV5_MMU_RADIX_300 */
870 val
[1] = 0x00; /* Hash */
873 /* TODO: TCG case, hash */
876 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
880 static void spapr_dt_chosen(sPAPRMachineState
*spapr
, void *fdt
)
882 MachineState
*machine
= MACHINE(spapr
);
884 const char *boot_device
= machine
->boot_order
;
885 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
887 char *bootlist
= get_boot_devices_list(&cb
, true);
889 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
891 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs", machine
->kernel_cmdline
));
892 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
893 spapr
->initrd_base
));
894 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
895 spapr
->initrd_base
+ spapr
->initrd_size
));
897 if (spapr
->kernel_size
) {
898 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
899 cpu_to_be64(spapr
->kernel_size
) };
901 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
902 &kprop
, sizeof(kprop
)));
903 if (spapr
->kernel_le
) {
904 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
908 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
910 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
911 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
912 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
914 if (cb
&& bootlist
) {
917 for (i
= 0; i
< cb
; i
++) {
918 if (bootlist
[i
] == '\n') {
922 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
925 if (boot_device
&& strlen(boot_device
)) {
926 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
929 if (!spapr
->has_graphics
&& stdout_path
) {
930 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
933 spapr_dt_ov5_platform_support(fdt
, chosen
);
939 static void spapr_dt_hypervisor(sPAPRMachineState
*spapr
, void *fdt
)
941 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
942 * KVM to work under pHyp with some guest co-operation */
944 uint8_t hypercall
[16];
946 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
947 /* indicate KVM hypercall interface */
948 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
949 if (kvmppc_has_cap_fixup_hcalls()) {
951 * Older KVM versions with older guest kernels were broken
952 * with the magic page, don't allow the guest to map it.
954 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
955 sizeof(hypercall
))) {
956 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
957 hypercall
, sizeof(hypercall
)));
962 static void *spapr_build_fdt(sPAPRMachineState
*spapr
,
966 MachineState
*machine
= MACHINE(qdev_get_machine());
967 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
968 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
973 int smt
= kvmppc_smt_threads();
975 fdt
= g_malloc0(FDT_MAX_SIZE
);
976 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
979 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
980 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
981 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
984 * Add info to guest to indentify which host is it being run on
985 * and what is the uuid of the guest
987 if (kvmppc_get_host_model(&buf
)) {
988 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
991 if (kvmppc_get_host_serial(&buf
)) {
992 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
996 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
998 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1000 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1004 if (qemu_get_vm_name()) {
1005 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1006 qemu_get_vm_name()));
1009 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1010 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1012 /* /interrupt controller */
1013 spapr_dt_xics(DIV_ROUND_UP(max_cpus
* smt
, smp_threads
), fdt
, PHANDLE_XICP
);
1015 ret
= spapr_populate_memory(spapr
, fdt
);
1017 error_report("couldn't setup memory nodes in fdt");
1022 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1024 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1025 ret
= spapr_rng_populate_dt(fdt
);
1027 error_report("could not set up rng device in the fdt");
1032 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1033 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
1035 error_report("couldn't setup PCI devices in fdt");
1041 spapr_populate_cpus_dt_node(fdt
, spapr
);
1043 if (smc
->dr_lmb_enabled
) {
1044 _FDT(spapr_drc_populate_dt(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1047 if (mc
->has_hotpluggable_cpus
) {
1048 int offset
= fdt_path_offset(fdt
, "/cpus");
1049 ret
= spapr_drc_populate_dt(fdt
, offset
, NULL
,
1050 SPAPR_DR_CONNECTOR_TYPE_CPU
);
1052 error_report("Couldn't set up CPU DR device tree properties");
1057 /* /event-sources */
1058 spapr_dt_events(spapr
, fdt
);
1061 spapr_dt_rtas(spapr
, fdt
);
1064 spapr_dt_chosen(spapr
, fdt
);
1067 if (kvm_enabled()) {
1068 spapr_dt_hypervisor(spapr
, fdt
);
1071 /* Build memory reserve map */
1072 if (spapr
->kernel_size
) {
1073 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1075 if (spapr
->initrd_size
) {
1076 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1079 /* ibm,client-architecture-support updates */
1080 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1082 error_report("couldn't setup CAS properties fdt");
1089 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1091 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1094 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1097 CPUPPCState
*env
= &cpu
->env
;
1099 /* The TCG path should also be holding the BQL at this point */
1100 g_assert(qemu_mutex_iothread_locked());
1103 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1104 env
->gpr
[3] = H_PRIVILEGE
;
1106 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1110 static uint64_t spapr_get_patbe(PPCVirtualHypervisor
*vhyp
)
1112 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1114 return spapr
->patb_entry
;
1117 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1118 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1119 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1120 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1121 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1124 * Get the fd to access the kernel htab, re-opening it if necessary
1126 static int get_htab_fd(sPAPRMachineState
*spapr
)
1128 if (spapr
->htab_fd
>= 0) {
1129 return spapr
->htab_fd
;
1132 spapr
->htab_fd
= kvmppc_get_htab_fd(false);
1133 if (spapr
->htab_fd
< 0) {
1134 error_report("Unable to open fd for reading hash table from KVM: %s",
1138 return spapr
->htab_fd
;
1141 void close_htab_fd(sPAPRMachineState
*spapr
)
1143 if (spapr
->htab_fd
>= 0) {
1144 close(spapr
->htab_fd
);
1146 spapr
->htab_fd
= -1;
1149 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1151 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1153 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1156 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1159 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1160 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1164 * HTAB is controlled by KVM. Fetch into temporary buffer
1166 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1167 kvmppc_read_hptes(hptes
, ptex
, n
);
1172 * HTAB is controlled by QEMU. Just point to the internally
1175 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1178 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1179 const ppc_hash_pte64_t
*hptes
,
1182 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1185 g_free((void *)hptes
);
1188 /* Nothing to do for qemu managed HPT */
1191 static void spapr_store_hpte(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1192 uint64_t pte0
, uint64_t pte1
)
1194 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1195 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1198 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1200 stq_p(spapr
->htab
+ offset
, pte0
);
1201 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1205 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1209 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1210 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1211 * that's much more than is needed for Linux guests */
1212 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1213 shift
= MAX(shift
, 18); /* Minimum architected size */
1214 shift
= MIN(shift
, 46); /* Maximum architected size */
1218 static void spapr_reallocate_hpt(sPAPRMachineState
*spapr
, int shift
,
1223 /* Clean up any HPT info from a previous boot */
1224 g_free(spapr
->htab
);
1226 spapr
->htab_shift
= 0;
1227 close_htab_fd(spapr
);
1229 rc
= kvmppc_reset_htab(shift
);
1231 /* kernel-side HPT needed, but couldn't allocate one */
1232 error_setg_errno(errp
, errno
,
1233 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1235 /* This is almost certainly fatal, but if the caller really
1236 * wants to carry on with shift == 0, it's welcome to try */
1237 } else if (rc
> 0) {
1238 /* kernel-side HPT allocated */
1241 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1245 spapr
->htab_shift
= shift
;
1248 /* kernel-side HPT not needed, allocate in userspace instead */
1249 size_t size
= 1ULL << shift
;
1252 spapr
->htab
= qemu_memalign(size
, size
);
1254 error_setg_errno(errp
, errno
,
1255 "Could not allocate HPT of order %d", shift
);
1259 memset(spapr
->htab
, 0, size
);
1260 spapr
->htab_shift
= shift
;
1262 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1263 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1268 void spapr_setup_hpt_and_vrma(sPAPRMachineState
*spapr
)
1270 spapr_reallocate_hpt(spapr
,
1271 spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
),
1273 if (spapr
->vrma_adjust
) {
1274 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(),
1277 /* We're setting up a hash table, so that means we're not radix */
1278 spapr
->patb_entry
= 0;
1281 static void find_unknown_sysbus_device(SysBusDevice
*sbdev
, void *opaque
)
1283 bool matched
= false;
1285 if (object_dynamic_cast(OBJECT(sbdev
), TYPE_SPAPR_PCI_HOST_BRIDGE
)) {
1290 error_report("Device %s is not supported by this machine yet.",
1291 qdev_fw_name(DEVICE(sbdev
)));
1296 static void ppc_spapr_reset(void)
1298 MachineState
*machine
= MACHINE(qdev_get_machine());
1299 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
1300 PowerPCCPU
*first_ppc_cpu
;
1301 uint32_t rtas_limit
;
1302 hwaddr rtas_addr
, fdt_addr
;
1306 /* Check for unknown sysbus devices */
1307 foreach_dynamic_sysbus_device(find_unknown_sysbus_device
, NULL
);
1309 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) {
1310 /* If using KVM with radix mode available, VCPUs can be started
1311 * without a HPT because KVM will start them in radix mode.
1312 * Set the GR bit in PATB so that we know there is no HPT. */
1313 spapr
->patb_entry
= PATBE1_GR
;
1315 spapr
->patb_entry
= 0;
1316 spapr_setup_hpt_and_vrma(spapr
);
1319 qemu_devices_reset();
1322 * We place the device tree and RTAS just below either the top of the RMA,
1323 * or just below 2GB, whichever is lowere, so that it can be
1324 * processed with 32-bit real mode code if necessary
1326 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
1327 rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1328 fdt_addr
= rtas_addr
- FDT_MAX_SIZE
;
1330 /* if this reset wasn't generated by CAS, we should reset our
1331 * negotiated options and start from scratch */
1332 if (!spapr
->cas_reboot
) {
1333 spapr_ovec_cleanup(spapr
->ov5_cas
);
1334 spapr
->ov5_cas
= spapr_ovec_new();
1337 fdt
= spapr_build_fdt(spapr
, rtas_addr
, spapr
->rtas_size
);
1339 spapr_load_rtas(spapr
, fdt
, rtas_addr
);
1343 /* Should only fail if we've built a corrupted tree */
1346 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1347 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1348 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1353 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1354 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1357 /* Set up the entry state */
1358 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1359 first_ppc_cpu
->env
.gpr
[3] = fdt_addr
;
1360 first_ppc_cpu
->env
.gpr
[5] = 0;
1361 first_cpu
->halted
= 0;
1362 first_ppc_cpu
->env
.nip
= SPAPR_ENTRY_POINT
;
1364 spapr
->cas_reboot
= false;
1367 static void spapr_create_nvram(sPAPRMachineState
*spapr
)
1369 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1370 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1373 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1377 qdev_init_nofail(dev
);
1379 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
1382 static void spapr_rtc_create(sPAPRMachineState
*spapr
)
1384 object_initialize(&spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
);
1385 object_property_add_child(OBJECT(spapr
), "rtc", OBJECT(&spapr
->rtc
),
1387 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1389 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1390 "date", &error_fatal
);
1393 /* Returns whether we want to use VGA or not */
1394 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1396 switch (vga_interface_type
) {
1403 return pci_vga_init(pci_bus
) != NULL
;
1406 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1411 static int spapr_post_load(void *opaque
, int version_id
)
1413 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1416 if (!object_dynamic_cast(OBJECT(spapr
->ics
), TYPE_ICS_KVM
)) {
1419 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1420 icp_resend(ICP(cpu
->intc
));
1424 /* In earlier versions, there was no separate qdev for the PAPR
1425 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1426 * So when migrating from those versions, poke the incoming offset
1427 * value into the RTC device */
1428 if (version_id
< 3) {
1429 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1435 static bool version_before_3(void *opaque
, int version_id
)
1437 return version_id
< 3;
1440 static bool spapr_ov5_cas_needed(void *opaque
)
1442 sPAPRMachineState
*spapr
= opaque
;
1443 sPAPROptionVector
*ov5_mask
= spapr_ovec_new();
1444 sPAPROptionVector
*ov5_legacy
= spapr_ovec_new();
1445 sPAPROptionVector
*ov5_removed
= spapr_ovec_new();
1448 /* Prior to the introduction of sPAPROptionVector, we had two option
1449 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1450 * Both of these options encode machine topology into the device-tree
1451 * in such a way that the now-booted OS should still be able to interact
1452 * appropriately with QEMU regardless of what options were actually
1453 * negotiatied on the source side.
1455 * As such, we can avoid migrating the CAS-negotiated options if these
1456 * are the only options available on the current machine/platform.
1457 * Since these are the only options available for pseries-2.7 and
1458 * earlier, this allows us to maintain old->new/new->old migration
1461 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1462 * via default pseries-2.8 machines and explicit command-line parameters.
1463 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1464 * of the actual CAS-negotiated values to continue working properly. For
1465 * example, availability of memory unplug depends on knowing whether
1466 * OV5_HP_EVT was negotiated via CAS.
1468 * Thus, for any cases where the set of available CAS-negotiatable
1469 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1470 * include the CAS-negotiated options in the migration stream.
1472 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1473 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1475 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1476 * the mask itself since in the future it's possible "legacy" bits may be
1477 * removed via machine options, which could generate a false positive
1478 * that breaks migration.
1480 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
1481 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
1483 spapr_ovec_cleanup(ov5_mask
);
1484 spapr_ovec_cleanup(ov5_legacy
);
1485 spapr_ovec_cleanup(ov5_removed
);
1490 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1491 .name
= "spapr_option_vector_ov5_cas",
1493 .minimum_version_id
= 1,
1494 .needed
= spapr_ov5_cas_needed
,
1495 .fields
= (VMStateField
[]) {
1496 VMSTATE_STRUCT_POINTER_V(ov5_cas
, sPAPRMachineState
, 1,
1497 vmstate_spapr_ovec
, sPAPROptionVector
),
1498 VMSTATE_END_OF_LIST()
1502 static bool spapr_patb_entry_needed(void *opaque
)
1504 sPAPRMachineState
*spapr
= opaque
;
1506 return !!spapr
->patb_entry
;
1509 static const VMStateDescription vmstate_spapr_patb_entry
= {
1510 .name
= "spapr_patb_entry",
1512 .minimum_version_id
= 1,
1513 .needed
= spapr_patb_entry_needed
,
1514 .fields
= (VMStateField
[]) {
1515 VMSTATE_UINT64(patb_entry
, sPAPRMachineState
),
1516 VMSTATE_END_OF_LIST()
1520 static const VMStateDescription vmstate_spapr
= {
1523 .minimum_version_id
= 1,
1524 .post_load
= spapr_post_load
,
1525 .fields
= (VMStateField
[]) {
1526 /* used to be @next_irq */
1527 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
1530 VMSTATE_UINT64_TEST(rtc_offset
, sPAPRMachineState
, version_before_3
),
1532 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPRMachineState
, 2),
1533 VMSTATE_END_OF_LIST()
1535 .subsections
= (const VMStateDescription
*[]) {
1536 &vmstate_spapr_ov5_cas
,
1537 &vmstate_spapr_patb_entry
,
1542 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
1544 sPAPRMachineState
*spapr
= opaque
;
1546 /* "Iteration" header */
1547 qemu_put_be32(f
, spapr
->htab_shift
);
1550 spapr
->htab_save_index
= 0;
1551 spapr
->htab_first_pass
= true;
1553 assert(kvm_enabled());
1560 static void htab_save_first_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1563 bool has_timeout
= max_ns
!= -1;
1564 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1565 int index
= spapr
->htab_save_index
;
1566 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1568 assert(spapr
->htab_first_pass
);
1573 /* Consume invalid HPTEs */
1574 while ((index
< htabslots
)
1575 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1576 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1580 /* Consume valid HPTEs */
1582 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
1583 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1584 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1588 if (index
> chunkstart
) {
1589 int n_valid
= index
- chunkstart
;
1591 qemu_put_be32(f
, chunkstart
);
1592 qemu_put_be16(f
, n_valid
);
1593 qemu_put_be16(f
, 0);
1594 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1595 HASH_PTE_SIZE_64
* n_valid
);
1598 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1602 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
1604 if (index
>= htabslots
) {
1605 assert(index
== htabslots
);
1607 spapr
->htab_first_pass
= false;
1609 spapr
->htab_save_index
= index
;
1612 static int htab_save_later_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1615 bool final
= max_ns
< 0;
1616 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
1617 int examined
= 0, sent
= 0;
1618 int index
= spapr
->htab_save_index
;
1619 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
1621 assert(!spapr
->htab_first_pass
);
1624 int chunkstart
, invalidstart
;
1626 /* Consume non-dirty HPTEs */
1627 while ((index
< htabslots
)
1628 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
1634 /* Consume valid dirty HPTEs */
1635 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
1636 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1637 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1638 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1643 invalidstart
= index
;
1644 /* Consume invalid dirty HPTEs */
1645 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
1646 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
1647 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
1648 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
1653 if (index
> chunkstart
) {
1654 int n_valid
= invalidstart
- chunkstart
;
1655 int n_invalid
= index
- invalidstart
;
1657 qemu_put_be32(f
, chunkstart
);
1658 qemu_put_be16(f
, n_valid
);
1659 qemu_put_be16(f
, n_invalid
);
1660 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1661 HASH_PTE_SIZE_64
* n_valid
);
1662 sent
+= index
- chunkstart
;
1664 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
1669 if (examined
>= htabslots
) {
1673 if (index
>= htabslots
) {
1674 assert(index
== htabslots
);
1677 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
1679 if (index
>= htabslots
) {
1680 assert(index
== htabslots
);
1684 spapr
->htab_save_index
= index
;
1686 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
1689 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1690 #define MAX_KVM_BUF_SIZE 2048
1692 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
1694 sPAPRMachineState
*spapr
= opaque
;
1698 /* Iteration header */
1699 qemu_put_be32(f
, 0);
1702 assert(kvm_enabled());
1704 fd
= get_htab_fd(spapr
);
1709 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
1713 } else if (spapr
->htab_first_pass
) {
1714 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
1716 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
1720 qemu_put_be32(f
, 0);
1721 qemu_put_be16(f
, 0);
1722 qemu_put_be16(f
, 0);
1727 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
1729 sPAPRMachineState
*spapr
= opaque
;
1732 /* Iteration header */
1733 qemu_put_be32(f
, 0);
1738 assert(kvm_enabled());
1740 fd
= get_htab_fd(spapr
);
1745 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
1750 if (spapr
->htab_first_pass
) {
1751 htab_save_first_pass(f
, spapr
, -1);
1753 htab_save_later_pass(f
, spapr
, -1);
1757 qemu_put_be32(f
, 0);
1758 qemu_put_be16(f
, 0);
1759 qemu_put_be16(f
, 0);
1764 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
1766 sPAPRMachineState
*spapr
= opaque
;
1767 uint32_t section_hdr
;
1770 if (version_id
< 1 || version_id
> 1) {
1771 error_report("htab_load() bad version");
1775 section_hdr
= qemu_get_be32(f
);
1778 Error
*local_err
= NULL
;
1780 /* First section gives the htab size */
1781 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
1783 error_report_err(local_err
);
1790 assert(kvm_enabled());
1792 fd
= kvmppc_get_htab_fd(true);
1794 error_report("Unable to open fd to restore KVM hash table: %s",
1801 uint16_t n_valid
, n_invalid
;
1803 index
= qemu_get_be32(f
);
1804 n_valid
= qemu_get_be16(f
);
1805 n_invalid
= qemu_get_be16(f
);
1807 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
1812 if ((index
+ n_valid
+ n_invalid
) >
1813 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
1814 /* Bad index in stream */
1816 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1817 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
1823 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
1824 HASH_PTE_SIZE_64
* n_valid
);
1827 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
1828 HASH_PTE_SIZE_64
* n_invalid
);
1835 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
1850 static void htab_cleanup(void *opaque
)
1852 sPAPRMachineState
*spapr
= opaque
;
1854 close_htab_fd(spapr
);
1857 static SaveVMHandlers savevm_htab_handlers
= {
1858 .save_live_setup
= htab_save_setup
,
1859 .save_live_iterate
= htab_save_iterate
,
1860 .save_live_complete_precopy
= htab_save_complete
,
1861 .cleanup
= htab_cleanup
,
1862 .load_state
= htab_load
,
1865 static void spapr_boot_set(void *opaque
, const char *boot_device
,
1868 MachineState
*machine
= MACHINE(qdev_get_machine());
1869 machine
->boot_order
= g_strdup(boot_device
);
1873 * Reset routine for LMB DR devices.
1875 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1876 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1877 * when it walks all its children devices. LMB devices reset occurs
1878 * as part of spapr_ppc_reset().
1880 static void spapr_drc_reset(void *opaque
)
1882 sPAPRDRConnector
*drc
= opaque
;
1883 DeviceState
*d
= DEVICE(drc
);
1890 static void spapr_create_lmb_dr_connectors(sPAPRMachineState
*spapr
)
1892 MachineState
*machine
= MACHINE(spapr
);
1893 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
1894 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
1897 for (i
= 0; i
< nr_lmbs
; i
++) {
1898 sPAPRDRConnector
*drc
;
1901 addr
= i
* lmb_size
+ spapr
->hotplug_memory
.base
;
1902 drc
= spapr_dr_connector_new(OBJECT(spapr
), SPAPR_DR_CONNECTOR_TYPE_LMB
,
1904 qemu_register_reset(spapr_drc_reset
, drc
);
1909 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1910 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1911 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1913 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
1917 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
1918 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
1919 " is not aligned to %llu MiB",
1921 SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
1925 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
1926 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
1927 " is not aligned to %llu MiB",
1929 SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
1933 for (i
= 0; i
< nb_numa_nodes
; i
++) {
1934 if (numa_info
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
1936 "Node %d memory size 0x%" PRIx64
1937 " is not aligned to %llu MiB",
1938 i
, numa_info
[i
].node_mem
,
1939 SPAPR_MEMORY_BLOCK_SIZE
/ M_BYTE
);
1945 /* find cpu slot in machine->possible_cpus by core_id */
1946 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
1948 int index
= id
/ smp_threads
;
1950 if (index
>= ms
->possible_cpus
->len
) {
1956 return &ms
->possible_cpus
->cpus
[index
];
1959 static void spapr_init_cpus(sPAPRMachineState
*spapr
)
1961 MachineState
*machine
= MACHINE(spapr
);
1962 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1963 char *type
= spapr_get_cpu_core_type(machine
->cpu_model
);
1964 int smt
= kvmppc_smt_threads();
1965 const CPUArchIdList
*possible_cpus
;
1966 int boot_cores_nr
= smp_cpus
/ smp_threads
;
1970 error_report("Unable to find sPAPR CPU Core definition");
1974 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
1975 if (mc
->has_hotpluggable_cpus
) {
1976 if (smp_cpus
% smp_threads
) {
1977 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1978 smp_cpus
, smp_threads
);
1981 if (max_cpus
% smp_threads
) {
1982 error_report("max_cpus (%u) must be multiple of threads (%u)",
1983 max_cpus
, smp_threads
);
1987 if (max_cpus
!= smp_cpus
) {
1988 error_report("This machine version does not support CPU hotplug");
1991 boot_cores_nr
= possible_cpus
->len
;
1994 for (i
= 0; i
< possible_cpus
->len
; i
++) {
1995 int core_id
= i
* smp_threads
;
1997 if (mc
->has_hotpluggable_cpus
) {
1998 sPAPRDRConnector
*drc
=
1999 spapr_dr_connector_new(OBJECT(spapr
),
2000 SPAPR_DR_CONNECTOR_TYPE_CPU
,
2001 (core_id
/ smp_threads
) * smt
);
2003 qemu_register_reset(spapr_drc_reset
, drc
);
2006 if (i
< boot_cores_nr
) {
2007 Object
*core
= object_new(type
);
2008 int nr_threads
= smp_threads
;
2010 /* Handle the partially filled core for older machine types */
2011 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2012 nr_threads
= smp_cpus
- i
* smp_threads
;
2015 object_property_set_int(core
, nr_threads
, "nr-threads",
2017 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2019 object_property_set_bool(core
, true, "realized", &error_fatal
);
2025 /* pSeries LPAR / sPAPR hardware init */
2026 static void ppc_spapr_init(MachineState
*machine
)
2028 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
2029 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2030 const char *kernel_filename
= machine
->kernel_filename
;
2031 const char *initrd_filename
= machine
->initrd_filename
;
2034 MemoryRegion
*sysmem
= get_system_memory();
2035 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2036 MemoryRegion
*rma_region
;
2038 hwaddr rma_alloc_size
;
2039 hwaddr node0_size
= spapr_node0_size();
2040 long load_limit
, fw_size
;
2043 msi_nonbroken
= true;
2045 QLIST_INIT(&spapr
->phbs
);
2047 /* Allocate RMA if necessary */
2048 rma_alloc_size
= kvmppc_alloc_rma(&rma
);
2050 if (rma_alloc_size
== -1) {
2051 error_report("Unable to create RMA");
2055 if (rma_alloc_size
&& (rma_alloc_size
< node0_size
)) {
2056 spapr
->rma_size
= rma_alloc_size
;
2058 spapr
->rma_size
= node0_size
;
2060 /* With KVM, we don't actually know whether KVM supports an
2061 * unbounded RMA (PR KVM) or is limited by the hash table size
2062 * (HV KVM using VRMA), so we always assume the latter
2064 * In that case, we also limit the initial allocations for RTAS
2065 * etc... to 256M since we have no way to know what the VRMA size
2066 * is going to be as it depends on the size of the hash table
2067 * isn't determined yet.
2069 if (kvm_enabled()) {
2070 spapr
->vrma_adjust
= 1;
2071 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2074 /* Actually we don't support unbounded RMA anymore since we
2075 * added proper emulation of HV mode. The max we can get is
2076 * 16G which also happens to be what we configure for PAPR
2077 * mode so make sure we don't do anything bigger than that
2079 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2082 if (spapr
->rma_size
> node0_size
) {
2083 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2088 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2089 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2091 /* Set up Interrupt Controller before we create the VCPUs */
2092 xics_system_init(machine
, XICS_IRQS_SPAPR
, &error_fatal
);
2094 /* Set up containers for ibm,client-set-architecture negotiated options */
2095 spapr
->ov5
= spapr_ovec_new();
2096 spapr
->ov5_cas
= spapr_ovec_new();
2098 if (smc
->dr_lmb_enabled
) {
2099 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2100 spapr_validate_node_memory(machine
, &error_fatal
);
2103 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2104 if (kvmppc_has_cap_mmu_radix()) {
2105 /* KVM always allows GTSE with radix... */
2106 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2108 /* ... but not with hash (currently). */
2110 /* advertise support for dedicated HP event source to guests */
2111 if (spapr
->use_hotplug_event_source
) {
2112 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2116 if (machine
->cpu_model
== NULL
) {
2117 machine
->cpu_model
= kvm_enabled() ? "host" : smc
->tcg_default_cpu
;
2120 ppc_cpu_parse_features(machine
->cpu_model
);
2122 spapr_init_cpus(spapr
);
2124 if (kvm_enabled()) {
2125 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2126 kvmppc_enable_logical_ci_hcalls();
2127 kvmppc_enable_set_mode_hcall();
2129 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2130 kvmppc_enable_clear_ref_mod_hcalls();
2134 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2136 memory_region_add_subregion(sysmem
, 0, ram
);
2138 if (rma_alloc_size
&& rma
) {
2139 rma_region
= g_new(MemoryRegion
, 1);
2140 memory_region_init_ram_ptr(rma_region
, NULL
, "ppc_spapr.rma",
2141 rma_alloc_size
, rma
);
2142 vmstate_register_ram_global(rma_region
);
2143 memory_region_add_subregion(sysmem
, 0, rma_region
);
2146 /* initialize hotplug memory address space */
2147 if (machine
->ram_size
< machine
->maxram_size
) {
2148 ram_addr_t hotplug_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2150 * Limit the number of hotpluggable memory slots to half the number
2151 * slots that KVM supports, leaving the other half for PCI and other
2152 * devices. However ensure that number of slots doesn't drop below 32.
2154 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2155 SPAPR_MAX_RAM_SLOTS
;
2157 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2158 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2160 if (machine
->ram_slots
> max_memslots
) {
2161 error_report("Specified number of memory slots %"
2162 PRIu64
" exceeds max supported %d",
2163 machine
->ram_slots
, max_memslots
);
2167 spapr
->hotplug_memory
.base
= ROUND_UP(machine
->ram_size
,
2168 SPAPR_HOTPLUG_MEM_ALIGN
);
2169 memory_region_init(&spapr
->hotplug_memory
.mr
, OBJECT(spapr
),
2170 "hotplug-memory", hotplug_mem_size
);
2171 memory_region_add_subregion(sysmem
, spapr
->hotplug_memory
.base
,
2172 &spapr
->hotplug_memory
.mr
);
2175 if (smc
->dr_lmb_enabled
) {
2176 spapr_create_lmb_dr_connectors(spapr
);
2179 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
2181 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2184 spapr
->rtas_size
= get_image_size(filename
);
2185 if (spapr
->rtas_size
< 0) {
2186 error_report("Could not get size of LPAR rtas '%s'", filename
);
2189 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
2190 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
2191 error_report("Could not load LPAR rtas '%s'", filename
);
2194 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
2195 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2196 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
2201 /* Set up RTAS event infrastructure */
2202 spapr_events_init(spapr
);
2204 /* Set up the RTC RTAS interfaces */
2205 spapr_rtc_create(spapr
);
2207 /* Set up VIO bus */
2208 spapr
->vio_bus
= spapr_vio_bus_init();
2210 for (i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
2211 if (serial_hds
[i
]) {
2212 spapr_vty_create(spapr
->vio_bus
, serial_hds
[i
]);
2216 /* We always have at least the nvram device on VIO */
2217 spapr_create_nvram(spapr
);
2220 spapr_pci_rtas_init();
2222 phb
= spapr_create_phb(spapr
, 0);
2224 for (i
= 0; i
< nb_nics
; i
++) {
2225 NICInfo
*nd
= &nd_table
[i
];
2228 nd
->model
= g_strdup("ibmveth");
2231 if (strcmp(nd
->model
, "ibmveth") == 0) {
2232 spapr_vlan_create(spapr
->vio_bus
, nd
);
2234 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2238 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2239 spapr_vscsi_create(spapr
->vio_bus
);
2243 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2244 spapr
->has_graphics
= true;
2245 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2249 if (smc
->use_ohci_by_default
) {
2250 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2252 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2255 if (spapr
->has_graphics
) {
2256 USBBus
*usb_bus
= usb_bus_find(-1);
2258 usb_create_simple(usb_bus
, "usb-kbd");
2259 usb_create_simple(usb_bus
, "usb-mouse");
2263 if (spapr
->rma_size
< (MIN_RMA_SLOF
<< 20)) {
2265 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2270 if (kernel_filename
) {
2271 uint64_t lowaddr
= 0;
2273 spapr
->kernel_size
= load_elf(kernel_filename
, translate_kernel_address
,
2274 NULL
, NULL
, &lowaddr
, NULL
, 1,
2275 PPC_ELF_MACHINE
, 0, 0);
2276 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2277 spapr
->kernel_size
= load_elf(kernel_filename
,
2278 translate_kernel_address
, NULL
, NULL
,
2279 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
2281 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2283 if (spapr
->kernel_size
< 0) {
2284 error_report("error loading %s: %s", kernel_filename
,
2285 load_elf_strerror(spapr
->kernel_size
));
2290 if (initrd_filename
) {
2291 /* Try to locate the initrd in the gap between the kernel
2292 * and the firmware. Add a bit of space just in case
2294 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
2295 + 0x1ffff) & ~0xffff;
2296 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2299 - spapr
->initrd_base
);
2300 if (spapr
->initrd_size
< 0) {
2301 error_report("could not load initial ram disk '%s'",
2308 if (bios_name
== NULL
) {
2309 bios_name
= FW_FILE_NAME
;
2311 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2313 error_report("Could not find LPAR firmware '%s'", bios_name
);
2316 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2318 error_report("Could not load LPAR firmware '%s'", filename
);
2323 /* FIXME: Should register things through the MachineState's qdev
2324 * interface, this is a legacy from the sPAPREnvironment structure
2325 * which predated MachineState but had a similar function */
2326 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
2327 register_savevm_live(NULL
, "spapr/htab", -1, 1,
2328 &savevm_htab_handlers
, spapr
);
2331 QTAILQ_INIT(&spapr
->ccs_list
);
2332 qemu_register_reset(spapr_ccs_reset_hook
, spapr
);
2334 qemu_register_boot_set(spapr_boot_set
, spapr
);
2336 if (kvm_enabled()) {
2337 /* to stop and start vmclock */
2338 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
2341 kvmppc_spapr_enable_inkernel_multitce();
2345 static int spapr_kvm_type(const char *vm_type
)
2351 if (!strcmp(vm_type
, "HV")) {
2355 if (!strcmp(vm_type
, "PR")) {
2359 error_report("Unknown kvm-type specified '%s'", vm_type
);
2364 * Implementation of an interface to adjust firmware path
2365 * for the bootindex property handling.
2367 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
2370 #define CAST(type, obj, name) \
2371 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2372 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
2373 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2376 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
2377 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
2378 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
2382 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2383 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2384 * in the top 16 bits of the 64-bit LUN
2386 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
2387 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2388 (uint64_t)id
<< 48);
2389 } else if (virtio
) {
2391 * We use SRP luns of the form 01000000 | (target << 8) | lun
2392 * in the top 32 bits of the 64-bit LUN
2393 * Note: the quote above is from SLOF and it is wrong,
2394 * the actual binding is:
2395 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2397 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
2398 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2399 (uint64_t)id
<< 32);
2402 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2403 * in the top 32 bits of the 64-bit LUN
2405 unsigned usb_port
= atoi(usb
->port
->path
);
2406 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
2407 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2408 (uint64_t)id
<< 32);
2413 * SLOF probes the USB devices, and if it recognizes that the device is a
2414 * storage device, it changes its name to "storage" instead of "usb-host",
2415 * and additionally adds a child node for the SCSI LUN, so the correct
2416 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2418 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
2419 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
2420 if (usb_host_dev_is_scsi_storage(usbdev
)) {
2421 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
2426 /* Replace "pci" with "pci@800000020000000" */
2427 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
2433 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
2435 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2437 return g_strdup(spapr
->kvm_type
);
2440 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
2442 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2444 g_free(spapr
->kvm_type
);
2445 spapr
->kvm_type
= g_strdup(value
);
2448 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
2450 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2452 return spapr
->use_hotplug_event_source
;
2455 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
2458 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2460 spapr
->use_hotplug_event_source
= value
;
2463 static void spapr_machine_initfn(Object
*obj
)
2465 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2467 spapr
->htab_fd
= -1;
2468 spapr
->use_hotplug_event_source
= true;
2469 object_property_add_str(obj
, "kvm-type",
2470 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
2471 object_property_set_description(obj
, "kvm-type",
2472 "Specifies the KVM virtualization mode (HV, PR)",
2474 object_property_add_bool(obj
, "modern-hotplug-events",
2475 spapr_get_modern_hotplug_events
,
2476 spapr_set_modern_hotplug_events
,
2478 object_property_set_description(obj
, "modern-hotplug-events",
2479 "Use dedicated hotplug event mechanism in"
2480 " place of standard EPOW events when possible"
2481 " (required for memory hot-unplug support)",
2485 static void spapr_machine_finalizefn(Object
*obj
)
2487 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2489 g_free(spapr
->kvm_type
);
2492 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
2494 cpu_synchronize_state(cs
);
2495 ppc_cpu_do_system_reset(cs
);
2498 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2503 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
2507 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
2508 uint32_t node
, bool dedicated_hp_event_source
,
2511 sPAPRDRConnector
*drc
;
2512 sPAPRDRConnectorClass
*drck
;
2513 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
2514 int i
, fdt_offset
, fdt_size
;
2516 uint64_t addr
= addr_start
;
2518 for (i
= 0; i
< nr_lmbs
; i
++) {
2519 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2520 addr
/SPAPR_MEMORY_BLOCK_SIZE
);
2523 fdt
= create_device_tree(&fdt_size
);
2524 fdt_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
2525 SPAPR_MEMORY_BLOCK_SIZE
);
2527 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2528 drck
->attach(drc
, dev
, fdt
, fdt_offset
, !dev
->hotplugged
, errp
);
2529 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
2530 if (!dev
->hotplugged
) {
2531 /* guests expect coldplugged LMBs to be pre-allocated */
2532 drck
->set_allocation_state(drc
, SPAPR_DR_ALLOCATION_STATE_USABLE
);
2533 drck
->set_isolation_state(drc
, SPAPR_DR_ISOLATION_STATE_UNISOLATED
);
2536 /* send hotplug notification to the
2537 * guest only in case of hotplugged memory
2539 if (dev
->hotplugged
) {
2540 if (dedicated_hp_event_source
) {
2541 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2542 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
2543 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2544 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2546 drck
->get_index(drc
));
2548 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2554 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2555 uint32_t node
, Error
**errp
)
2557 Error
*local_err
= NULL
;
2558 sPAPRMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
2559 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
2560 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
2561 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
);
2562 uint64_t align
= memory_region_get_alignment(mr
);
2563 uint64_t size
= memory_region_size(mr
);
2567 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2568 error_setg(&local_err
, "Hotplugged memory size must be a multiple of "
2569 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE
/M_BYTE
);
2573 mem_dev
= object_property_get_str(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
, NULL
);
2574 if (mem_dev
&& !kvmppc_is_mem_backend_page_size_ok(mem_dev
)) {
2575 error_setg(&local_err
, "Memory backend has bad page size. "
2576 "Use 'memory-backend-file' with correct mem-path.");
2580 pc_dimm_memory_plug(dev
, &ms
->hotplug_memory
, mr
, align
, &local_err
);
2585 addr
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
, &local_err
);
2587 pc_dimm_memory_unplug(dev
, &ms
->hotplug_memory
, mr
);
2591 spapr_add_lmbs(dev
, addr
, size
, node
,
2592 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
2596 error_propagate(errp
, local_err
);
2599 typedef struct sPAPRDIMMState
{
2603 static void spapr_lmb_release(DeviceState
*dev
, void *opaque
)
2605 sPAPRDIMMState
*ds
= (sPAPRDIMMState
*)opaque
;
2606 HotplugHandler
*hotplug_ctrl
;
2608 if (--ds
->nr_lmbs
) {
2615 * Now that all the LMBs have been removed by the guest, call the
2616 * pc-dimm unplug handler to cleanup up the pc-dimm device.
2618 hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
2619 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
2622 static void spapr_del_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
2625 sPAPRDRConnector
*drc
;
2626 sPAPRDRConnectorClass
*drck
;
2627 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
2629 sPAPRDIMMState
*ds
= g_malloc0(sizeof(sPAPRDIMMState
));
2630 uint64_t addr
= addr_start
;
2632 ds
->nr_lmbs
= nr_lmbs
;
2633 for (i
= 0; i
< nr_lmbs
; i
++) {
2634 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2635 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
2638 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2639 drck
->detach(drc
, dev
, spapr_lmb_release
, ds
, errp
);
2640 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
2643 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2644 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
2645 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2646 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
2648 drck
->get_index(drc
));
2651 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2654 sPAPRMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
2655 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
2656 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
2657 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
);
2659 pc_dimm_memory_unplug(dev
, &ms
->hotplug_memory
, mr
);
2660 object_unparent(OBJECT(dev
));
2663 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
2664 DeviceState
*dev
, Error
**errp
)
2666 Error
*local_err
= NULL
;
2667 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
2668 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
2669 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
);
2670 uint64_t size
= memory_region_size(mr
);
2673 addr
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
, &local_err
);
2678 spapr_del_lmbs(dev
, addr
, size
, &error_abort
);
2680 error_propagate(errp
, local_err
);
2683 void *spapr_populate_hotplug_cpu_dt(CPUState
*cs
, int *fdt_offset
,
2684 sPAPRMachineState
*spapr
)
2686 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2687 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
2688 int id
= ppc_get_vcpu_dt_id(cpu
);
2690 int offset
, fdt_size
;
2693 fdt
= create_device_tree(&fdt_size
);
2694 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
2695 offset
= fdt_add_subnode(fdt
, 0, nodename
);
2697 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
2700 *fdt_offset
= offset
;
2704 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2707 MachineState
*ms
= MACHINE(qdev_get_machine());
2708 CPUCore
*cc
= CPU_CORE(dev
);
2709 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
2711 core_slot
->cpu
= NULL
;
2712 object_unparent(OBJECT(dev
));
2715 static void spapr_core_release(DeviceState
*dev
, void *opaque
)
2717 HotplugHandler
*hotplug_ctrl
;
2719 hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
2720 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
2724 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2728 sPAPRDRConnector
*drc
;
2729 sPAPRDRConnectorClass
*drck
;
2730 Error
*local_err
= NULL
;
2731 CPUCore
*cc
= CPU_CORE(dev
);
2732 int smt
= kvmppc_smt_threads();
2734 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
2735 error_setg(errp
, "Unable to find CPU core with core-id: %d",
2740 error_setg(errp
, "Boot CPU core may not be unplugged");
2744 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU
, index
* smt
);
2747 drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2748 drck
->detach(drc
, dev
, spapr_core_release
, NULL
, &local_err
);
2750 error_propagate(errp
, local_err
);
2754 spapr_hotplug_req_remove_by_index(drc
);
2757 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2760 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
2761 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
2762 sPAPRCPUCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
2763 CPUCore
*cc
= CPU_CORE(dev
);
2764 CPUState
*cs
= CPU(core
->threads
);
2765 sPAPRDRConnector
*drc
;
2766 Error
*local_err
= NULL
;
2769 int smt
= kvmppc_smt_threads();
2770 CPUArchId
*core_slot
;
2773 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
2775 error_setg(errp
, "Unable to find CPU core with core-id: %d",
2779 drc
= spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU
, index
* smt
);
2781 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
2784 * Setup CPU DT entries only for hotplugged CPUs. For boot time or
2785 * coldplugged CPUs DT entries are setup in spapr_build_fdt().
2787 if (dev
->hotplugged
) {
2788 fdt
= spapr_populate_hotplug_cpu_dt(cs
, &fdt_offset
, spapr
);
2792 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2793 drck
->attach(drc
, dev
, fdt
, fdt_offset
, !dev
->hotplugged
, &local_err
);
2796 error_propagate(errp
, local_err
);
2801 if (dev
->hotplugged
) {
2803 * Send hotplug notification interrupt to the guest only in case
2804 * of hotplugged CPUs.
2806 spapr_hotplug_req_add_by_index(drc
);
2809 * Set the right DRC states for cold plugged CPU.
2812 sPAPRDRConnectorClass
*drck
= SPAPR_DR_CONNECTOR_GET_CLASS(drc
);
2813 drck
->set_allocation_state(drc
, SPAPR_DR_ALLOCATION_STATE_USABLE
);
2814 drck
->set_isolation_state(drc
, SPAPR_DR_ISOLATION_STATE_UNISOLATED
);
2817 core_slot
->cpu
= OBJECT(dev
);
2820 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
2823 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
2824 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
2825 Error
*local_err
= NULL
;
2826 CPUCore
*cc
= CPU_CORE(dev
);
2827 char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_model
);
2828 const char *type
= object_get_typename(OBJECT(dev
));
2829 CPUArchId
*core_slot
;
2832 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
2833 error_setg(&local_err
, "CPU hotplug not supported for this machine");
2837 if (strcmp(base_core_type
, type
)) {
2838 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
2842 if (cc
->core_id
% smp_threads
) {
2843 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
2847 if (cc
->nr_threads
!= smp_threads
) {
2848 error_setg(errp
, "invalid nr-threads %d, must be %d",
2849 cc
->nr_threads
, smp_threads
);
2853 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
2855 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
2859 if (core_slot
->cpu
) {
2860 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
2865 g_free(base_core_type
);
2866 error_propagate(errp
, local_err
);
2869 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
2870 DeviceState
*dev
, Error
**errp
)
2872 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2874 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2877 if (!smc
->dr_lmb_enabled
) {
2878 error_setg(errp
, "Memory hotplug not supported for this machine");
2881 node
= object_property_get_int(OBJECT(dev
), PC_DIMM_NODE_PROP
, errp
);
2885 if (node
< 0 || node
>= MAX_NODES
) {
2886 error_setg(errp
, "Invaild node %d", node
);
2891 * Currently PowerPC kernel doesn't allow hot-adding memory to
2892 * memory-less node, but instead will silently add the memory
2893 * to the first node that has some memory. This causes two
2894 * unexpected behaviours for the user.
2896 * - Memory gets hotplugged to a different node than what the user
2898 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2899 * to memory-less node, a reboot will set things accordingly
2900 * and the previously hotplugged memory now ends in the right node.
2901 * This appears as if some memory moved from one node to another.
2903 * So until kernel starts supporting memory hotplug to memory-less
2904 * nodes, just prevent such attempts upfront in QEMU.
2906 if (nb_numa_nodes
&& !numa_info
[node
].node_mem
) {
2907 error_setg(errp
, "Can't hotplug memory to memory-less node %d",
2912 spapr_memory_plug(hotplug_dev
, dev
, node
, errp
);
2913 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
2914 spapr_core_plug(hotplug_dev
, dev
, errp
);
2918 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
2919 DeviceState
*dev
, Error
**errp
)
2921 sPAPRMachineState
*sms
= SPAPR_MACHINE(qdev_get_machine());
2922 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
2924 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2925 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
2926 spapr_memory_unplug(hotplug_dev
, dev
, errp
);
2928 error_setg(errp
, "Memory hot unplug not supported for this guest");
2930 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
2931 if (!mc
->has_hotpluggable_cpus
) {
2932 error_setg(errp
, "CPU hot unplug not supported on this machine");
2935 spapr_core_unplug(hotplug_dev
, dev
, errp
);
2939 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
2940 DeviceState
*dev
, Error
**errp
)
2942 sPAPRMachineState
*sms
= SPAPR_MACHINE(qdev_get_machine());
2943 MachineClass
*mc
= MACHINE_GET_CLASS(qdev_get_machine());
2945 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
2946 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
2947 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
2949 /* NOTE: this means there is a window after guest reset, prior to
2950 * CAS negotiation, where unplug requests will fail due to the
2951 * capability not being detected yet. This is a bit different than
2952 * the case with PCI unplug, where the events will be queued and
2953 * eventually handled by the guest after boot
2955 error_setg(errp
, "Memory hot unplug not supported for this guest");
2957 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
2958 if (!mc
->has_hotpluggable_cpus
) {
2959 error_setg(errp
, "CPU hot unplug not supported on this machine");
2962 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
2966 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
2967 DeviceState
*dev
, Error
**errp
)
2969 if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
2970 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
2974 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
2977 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
2978 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
2979 return HOTPLUG_HANDLER(machine
);
2984 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index
)
2986 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2987 * socket means much for the paravirtualized PAPR platform) */
2988 return cpu_index
/ smp_threads
/ smp_cores
;
2991 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
2994 int spapr_max_cores
= max_cpus
/ smp_threads
;
2995 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2997 if (!mc
->has_hotpluggable_cpus
) {
2998 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
3000 if (machine
->possible_cpus
) {
3001 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
3002 return machine
->possible_cpus
;
3005 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
3006 sizeof(CPUArchId
) * spapr_max_cores
);
3007 machine
->possible_cpus
->len
= spapr_max_cores
;
3008 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
3009 int core_id
= i
* smp_threads
;
3011 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
3012 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
3013 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
3014 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
3015 /* TODO: add 'has_node/node' here to describe
3016 to which node core belongs */
3018 return machine
->possible_cpus
;
3021 static void spapr_phb_placement(sPAPRMachineState
*spapr
, uint32_t index
,
3022 uint64_t *buid
, hwaddr
*pio
,
3023 hwaddr
*mmio32
, hwaddr
*mmio64
,
3024 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
3027 * New-style PHB window placement.
3029 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3030 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3033 * Some guest kernels can't work with MMIO windows above 1<<46
3034 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3036 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3037 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3038 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3039 * 1TiB 64-bit MMIO windows for each PHB.
3041 const uint64_t base_buid
= 0x800000020000000ULL
;
3042 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3043 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3046 /* Sanity check natural alignments */
3047 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3048 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3049 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
3050 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
3051 /* Sanity check bounds */
3052 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
3053 SPAPR_PCI_MEM32_WIN_SIZE
);
3054 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
3055 SPAPR_PCI_MEM64_WIN_SIZE
);
3057 if (index
>= SPAPR_MAX_PHBS
) {
3058 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
3059 SPAPR_MAX_PHBS
- 1);
3063 *buid
= base_buid
+ index
;
3064 for (i
= 0; i
< n_dma
; ++i
) {
3065 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
3068 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
3069 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
3070 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
3073 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
3075 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3077 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
3080 static void spapr_ics_resend(XICSFabric
*dev
)
3082 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3084 ics_resend(spapr
->ics
);
3087 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int cpu_dt_id
)
3089 PowerPCCPU
*cpu
= ppc_get_vcpu_by_dt_id(cpu_dt_id
);
3091 return cpu
? ICP(cpu
->intc
) : NULL
;
3094 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
3097 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3101 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3103 icp_pic_print_info(ICP(cpu
->intc
), mon
);
3106 ics_pic_print_info(spapr
->ics
, mon
);
3109 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
3111 MachineClass
*mc
= MACHINE_CLASS(oc
);
3112 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
3113 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
3114 NMIClass
*nc
= NMI_CLASS(oc
);
3115 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
3116 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
3117 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
3118 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
3120 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
3123 * We set up the default / latest behaviour here. The class_init
3124 * functions for the specific versioned machine types can override
3125 * these details for backwards compatibility
3127 mc
->init
= ppc_spapr_init
;
3128 mc
->reset
= ppc_spapr_reset
;
3129 mc
->block_default_type
= IF_SCSI
;
3130 mc
->max_cpus
= 1024;
3131 mc
->no_parallel
= 1;
3132 mc
->default_boot_order
= "";
3133 mc
->default_ram_size
= 512 * M_BYTE
;
3134 mc
->kvm_type
= spapr_kvm_type
;
3135 mc
->has_dynamic_sysbus
= true;
3136 mc
->pci_allow_0_address
= true;
3137 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
3138 hc
->pre_plug
= spapr_machine_device_pre_plug
;
3139 hc
->plug
= spapr_machine_device_plug
;
3140 hc
->unplug
= spapr_machine_device_unplug
;
3141 mc
->cpu_index_to_socket_id
= spapr_cpu_index_to_socket_id
;
3142 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
3143 hc
->unplug_request
= spapr_machine_device_unplug_request
;
3145 smc
->dr_lmb_enabled
= true;
3146 smc
->tcg_default_cpu
= "POWER8";
3147 mc
->has_hotpluggable_cpus
= true;
3148 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
3149 nc
->nmi_monitor_handler
= spapr_nmi
;
3150 smc
->phb_placement
= spapr_phb_placement
;
3151 vhc
->hypercall
= emulate_spapr_hypercall
;
3152 vhc
->hpt_mask
= spapr_hpt_mask
;
3153 vhc
->map_hptes
= spapr_map_hptes
;
3154 vhc
->unmap_hptes
= spapr_unmap_hptes
;
3155 vhc
->store_hpte
= spapr_store_hpte
;
3156 vhc
->get_patbe
= spapr_get_patbe
;
3157 xic
->ics_get
= spapr_ics_get
;
3158 xic
->ics_resend
= spapr_ics_resend
;
3159 xic
->icp_get
= spapr_icp_get
;
3160 ispc
->print_info
= spapr_pic_print_info
;
3161 /* Force NUMA node memory size to be a multiple of
3162 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3163 * in which LMBs are represented and hot-added
3165 mc
->numa_mem_align_shift
= 28;
3168 static const TypeInfo spapr_machine_info
= {
3169 .name
= TYPE_SPAPR_MACHINE
,
3170 .parent
= TYPE_MACHINE
,
3172 .instance_size
= sizeof(sPAPRMachineState
),
3173 .instance_init
= spapr_machine_initfn
,
3174 .instance_finalize
= spapr_machine_finalizefn
,
3175 .class_size
= sizeof(sPAPRMachineClass
),
3176 .class_init
= spapr_machine_class_init
,
3177 .interfaces
= (InterfaceInfo
[]) {
3178 { TYPE_FW_PATH_PROVIDER
},
3180 { TYPE_HOTPLUG_HANDLER
},
3181 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
3182 { TYPE_XICS_FABRIC
},
3183 { TYPE_INTERRUPT_STATS_PROVIDER
},
3188 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3189 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3192 MachineClass *mc = MACHINE_CLASS(oc); \
3193 spapr_machine_##suffix##_class_options(mc); \
3195 mc->alias = "pseries"; \
3196 mc->is_default = 1; \
3199 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3201 MachineState *machine = MACHINE(obj); \
3202 spapr_machine_##suffix##_instance_options(machine); \
3204 static const TypeInfo spapr_machine_##suffix##_info = { \
3205 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3206 .parent = TYPE_SPAPR_MACHINE, \
3207 .class_init = spapr_machine_##suffix##_class_init, \
3208 .instance_init = spapr_machine_##suffix##_instance_init, \
3210 static void spapr_machine_register_##suffix(void) \
3212 type_register(&spapr_machine_##suffix##_info); \
3214 type_init(spapr_machine_register_##suffix)
3219 static void spapr_machine_2_10_instance_options(MachineState
*machine
)
3223 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
3225 /* Defaults for the latest behaviour inherited from the base class */
3228 DEFINE_SPAPR_MACHINE(2_10
, "2.10", true);
3233 #define SPAPR_COMPAT_2_9 \
3236 static void spapr_machine_2_9_instance_options(MachineState
*machine
)
3238 spapr_machine_2_10_instance_options(machine
);
3241 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
3243 spapr_machine_2_10_class_options(mc
);
3244 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_9
);
3247 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
3252 #define SPAPR_COMPAT_2_8 \
3255 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3256 .property = "pcie-extended-configuration-space", \
3260 static void spapr_machine_2_8_instance_options(MachineState
*machine
)
3262 spapr_machine_2_9_instance_options(machine
);
3265 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
3267 spapr_machine_2_9_class_options(mc
);
3268 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_8
);
3269 mc
->numa_mem_align_shift
= 23;
3272 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
3277 #define SPAPR_COMPAT_2_7 \
3280 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3281 .property = "mem_win_size", \
3282 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
3285 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3286 .property = "mem64_win_size", \
3290 .driver = TYPE_POWERPC_CPU, \
3291 .property = "pre-2.8-migration", \
3295 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
3296 .property = "pre-2.8-migration", \
3300 static void phb_placement_2_7(sPAPRMachineState
*spapr
, uint32_t index
,
3301 uint64_t *buid
, hwaddr
*pio
,
3302 hwaddr
*mmio32
, hwaddr
*mmio64
,
3303 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
3305 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
3306 const uint64_t base_buid
= 0x800000020000000ULL
;
3307 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
3308 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
3309 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
3310 const uint32_t max_index
= 255;
3311 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
3313 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
3314 hwaddr phb0_base
, phb_base
;
3317 /* Do we have hotpluggable memory? */
3318 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
3319 /* Can't just use maxram_size, because there may be an
3320 * alignment gap between normal and hotpluggable memory
3322 ram_top
= spapr
->hotplug_memory
.base
+
3323 memory_region_size(&spapr
->hotplug_memory
.mr
);
3326 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
3328 if (index
> max_index
) {
3329 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
3334 *buid
= base_buid
+ index
;
3335 for (i
= 0; i
< n_dma
; ++i
) {
3336 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
3339 phb_base
= phb0_base
+ index
* phb_spacing
;
3340 *pio
= phb_base
+ pio_offset
;
3341 *mmio32
= phb_base
+ mmio_offset
;
3343 * We don't set the 64-bit MMIO window, relying on the PHB's
3344 * fallback behaviour of automatically splitting a large "32-bit"
3345 * window into contiguous 32-bit and 64-bit windows
3349 static void spapr_machine_2_7_instance_options(MachineState
*machine
)
3351 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
3353 spapr_machine_2_8_instance_options(machine
);
3354 spapr
->use_hotplug_event_source
= false;
3357 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
3359 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3361 spapr_machine_2_8_class_options(mc
);
3362 smc
->tcg_default_cpu
= "POWER7";
3363 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_7
);
3364 smc
->phb_placement
= phb_placement_2_7
;
3367 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
3372 #define SPAPR_COMPAT_2_6 \
3375 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3377 .value = stringify(off),\
3380 static void spapr_machine_2_6_instance_options(MachineState
*machine
)
3382 spapr_machine_2_7_instance_options(machine
);
3385 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
3387 spapr_machine_2_7_class_options(mc
);
3388 mc
->has_hotpluggable_cpus
= false;
3389 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_6
);
3392 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
3397 #define SPAPR_COMPAT_2_5 \
3400 .driver = "spapr-vlan", \
3401 .property = "use-rx-buffer-pools", \
3405 static void spapr_machine_2_5_instance_options(MachineState
*machine
)
3407 spapr_machine_2_6_instance_options(machine
);
3410 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
3412 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3414 spapr_machine_2_6_class_options(mc
);
3415 smc
->use_ohci_by_default
= true;
3416 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_5
);
3419 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
3424 #define SPAPR_COMPAT_2_4 \
3427 static void spapr_machine_2_4_instance_options(MachineState
*machine
)
3429 spapr_machine_2_5_instance_options(machine
);
3432 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
3434 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3436 spapr_machine_2_5_class_options(mc
);
3437 smc
->dr_lmb_enabled
= false;
3438 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_4
);
3441 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
3446 #define SPAPR_COMPAT_2_3 \
3449 .driver = "spapr-pci-host-bridge",\
3450 .property = "dynamic-reconfiguration",\
3454 static void spapr_machine_2_3_instance_options(MachineState
*machine
)
3456 spapr_machine_2_4_instance_options(machine
);
3457 savevm_skip_section_footers();
3458 global_state_set_optional();
3459 savevm_skip_configuration();
3462 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
3464 spapr_machine_2_4_class_options(mc
);
3465 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_3
);
3467 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
3473 #define SPAPR_COMPAT_2_2 \
3476 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
3477 .property = "mem_win_size",\
3478 .value = "0x20000000",\
3481 static void spapr_machine_2_2_instance_options(MachineState
*machine
)
3483 spapr_machine_2_3_instance_options(machine
);
3484 machine
->suppress_vmdesc
= true;
3487 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
3489 spapr_machine_2_3_class_options(mc
);
3490 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_2
);
3492 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
3497 #define SPAPR_COMPAT_2_1 \
3500 static void spapr_machine_2_1_instance_options(MachineState
*machine
)
3502 spapr_machine_2_2_instance_options(machine
);
3505 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
3507 spapr_machine_2_2_class_options(mc
);
3508 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_1
);
3510 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
3512 static void spapr_machine_register_types(void)
3514 type_register_static(&spapr_machine_info
);
3517 type_init(spapr_machine_register_types
)