include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "hw/qdev.h"
   5 #include "exec/memory.h"
   6 #include "sysemu/dma.h"
   7
   8 /* PCI includes legacy ISA access.  */
   9 #include "hw/isa/isa.h"
  10
  11 #include "hw/pci/pcie.h"
  12
  13 extern bool pci_available;
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_BUS_NUM(x)          (((x) >> 8) & 0xff)
  19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  21 #define PCI_BUILD_BDF(bus, devfn)     ((bus << 8) | (devfn))
  22 #define PCI_BUS_MAX             256
  23 #define PCI_DEVFN_MAX           256
  24 #define PCI_SLOT_MAX            32
  25 #define PCI_FUNC_MAX            8
  26
  27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  28 #include "hw/pci/pci_ids.h"
  29
  30 /* QEMU-specific Vendor and Device ID definitions */
  31
  32 /* IBM (0x1014) */
  33 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  34 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  35
  36 /* Hitachi (0x1054) */
  37 #define PCI_VENDOR_ID_HITACHI            0x1054
  38 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  39
  40 /* Apple (0x106b) */
  41 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  45 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  46
  47 /* Realtek (0x10ec) */
  48 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  49
  50 /* Xilinx (0x10ee) */
  51 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  52
  53 /* Marvell (0x11ab) */
  54 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  55
  56 /* QEMU/Bochs VGA (0x1234) */
  57 #define PCI_VENDOR_ID_QEMU               0x1234
  58 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  59
  60 /* VMWare (0x15ad) */
  61 #define PCI_VENDOR_ID_VMWARE             0x15ad
  62 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  63 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  64 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  65 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  66 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
  67 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  68 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  69
  70 /* Intel (0x8086) */
  71 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  72 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  73 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  74
  75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  76 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  78 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  79
  80 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  81 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  82 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  84 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  85 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  86 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  87 #define PCI_DEVICE_ID_VIRTIO_VSOCK       0x1012
  88
  89 #define PCI_VENDOR_ID_REDHAT             0x1b36
  90 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  91 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  92 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  93 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  94 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
  95 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
  96 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
  97 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
  98 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
  99 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
 100 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
 101 #define PCI_DEVICE_ID_REDHAT_PCIE_RP     0x000c
 102 #define PCI_DEVICE_ID_REDHAT_XHCI        0x000d
 103 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
 104 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
 105
 106 #define FMT_PCIBUS                      PRIx64
 107
 108 typedef uint64_t pcibus_t;
 109
 110 struct PCIHostDeviceAddress {
 111     unsigned int domain;
 112     unsigned int bus;
 113     unsigned int slot;
 114     unsigned int function;
 115 };
 116
 117 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 118                                 uint32_t address, uint32_t data, int len);
 119 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 120                                    uint32_t address, int len);
 121 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 122                                 pcibus_t addr, pcibus_t size, int type);
 123 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 124
 125 typedef struct PCIIORegion {
 126     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 127 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 128     pcibus_t size;
 129     uint8_t type;
 130     MemoryRegion *memory;
 131     MemoryRegion *address_space;
 132 } PCIIORegion;
 133
 134 #define PCI_ROM_SLOT 6
 135 #define PCI_NUM_REGIONS 7
 136
 137 enum {
 138     QEMU_PCI_VGA_MEM,
 139     QEMU_PCI_VGA_IO_LO,
 140     QEMU_PCI_VGA_IO_HI,
 141     QEMU_PCI_VGA_NUM_REGIONS,
 142 };
 143
 144 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 145 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 146 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 147 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 148 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 149 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 150
 151 #include "hw/pci/pci_regs.h"
 152
 153 /* PCI HEADER_TYPE */
 154 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 155
 156 /* Size of the standard PCI config header */
 157 #define PCI_CONFIG_HEADER_SIZE 0x40
 158 /* Size of the standard PCI config space */
 159 #define PCI_CONFIG_SPACE_SIZE 0x100
 160 /* Size of the standard PCIe config space: 4KB */
 161 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 162
 163 #define PCI_NUM_PINS 4 /* A-D */
 164
 165 /* Bits in cap_present field. */
 166 enum {
 167     QEMU_PCI_CAP_MSI = 0x1,
 168     QEMU_PCI_CAP_MSIX = 0x2,
 169     QEMU_PCI_CAP_EXPRESS = 0x4,
 170
 171     /* multifunction capable device */
 172 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 173     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 174
 175     /* command register SERR bit enabled */
 176 #define QEMU_PCI_CAP_SERR_BITNR 4
 177     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 178     /* Standard hot plug controller. */
 179 #define QEMU_PCI_SHPC_BITNR 5
 180     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 181 #define QEMU_PCI_SLOTID_BITNR 6
 182     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 183     /* PCI Express capability - Power Controller Present */
 184 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
 185     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
 186     /* Link active status in endpoint capability is always set */
 187 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
 188     QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
 189 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
 190     QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
 191 };
 192
 193 #define TYPE_PCI_DEVICE "pci-device"
 194 #define PCI_DEVICE(obj) \
 195      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 196 #define PCI_DEVICE_CLASS(klass) \
 197      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 198 #define PCI_DEVICE_GET_CLASS(obj) \
 199      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 200
 201 /* Implemented by devices that can be plugged on PCI Express buses */
 202 #define INTERFACE_PCIE_DEVICE "pci-express-device"
 203
 204 /* Implemented by devices that can be plugged on Conventional PCI buses */
 205 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
 206
 207 typedef struct PCIINTxRoute {
 208     enum {
 209         PCI_INTX_ENABLED,
 210         PCI_INTX_INVERTED,
 211         PCI_INTX_DISABLED,
 212     } mode;
 213     int irq;
 214 } PCIINTxRoute;
 215
 216 typedef struct PCIDeviceClass {
 217     DeviceClass parent_class;
 218
 219     void (*realize)(PCIDevice *dev, Error **errp);
 220     int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */
 221     PCIUnregisterFunc *exit;
 222     PCIConfigReadFunc *config_read;
 223     PCIConfigWriteFunc *config_write;
 224
 225     uint16_t vendor_id;
 226     uint16_t device_id;
 227     uint8_t revision;
 228     uint16_t class_id;
 229     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 230     uint16_t subsystem_id;              /* only for header type = 0 */
 231
 232     /*
 233      * pci-to-pci bridge or normal device.
 234      * This doesn't mean pci host switch.
 235      * When card bus bridge is supported, this would be enhanced.
 236      */
 237     int is_bridge;
 238
 239     /* pcie stuff */
 240     int is_express;   /* is this device pci express? */
 241
 242     /* rom bar */
 243     const char *romfile;
 244 } PCIDeviceClass;
 245
 246 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 247 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 248                                       MSIMessage msg);
 249 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 250 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 251                                       unsigned int vector_start,
 252                                       unsigned int vector_end);
 253
 254 enum PCIReqIDType {
 255     PCI_REQ_ID_INVALID = 0,
 256     PCI_REQ_ID_BDF,
 257     PCI_REQ_ID_SECONDARY_BUS,
 258     PCI_REQ_ID_MAX,
 259 };
 260 typedef enum PCIReqIDType PCIReqIDType;
 261
 262 struct PCIReqIDCache {
 263     PCIDevice *dev;
 264     PCIReqIDType type;
 265 };
 266 typedef struct PCIReqIDCache PCIReqIDCache;
 267
 268 struct PCIDevice {
 269     DeviceState qdev;
 270
 271     /* PCI config space */
 272     uint8_t *config;
 273
 274     /* Used to enable config checks on load. Note that writable bits are
 275      * never checked even if set in cmask. */
 276     uint8_t *cmask;
 277
 278     /* Used to implement R/W bytes */
 279     uint8_t *wmask;
 280
 281     /* Used to implement RW1C(Write 1 to Clear) bytes */
 282     uint8_t *w1cmask;
 283
 284     /* Used to allocate config space for capabilities. */
 285     uint8_t *used;
 286
 287     /* the following fields are read only */
 288     PCIBus *bus;
 289     int32_t devfn;
 290     /* Cached device to fetch requester ID from, to avoid the PCI
 291      * tree walking every time we invoke PCI request (e.g.,
 292      * MSI). For conventional PCI root complex, this field is
 293      * meaningless. */
 294     PCIReqIDCache requester_id_cache;
 295     char name[64];
 296     PCIIORegion io_regions[PCI_NUM_REGIONS];
 297     AddressSpace bus_master_as;
 298     MemoryRegion bus_master_container_region;
 299     MemoryRegion bus_master_enable_region;
 300
 301     /* do not access the following fields */
 302     PCIConfigReadFunc *config_read;
 303     PCIConfigWriteFunc *config_write;
 304
 305     /* Legacy PCI VGA regions */
 306     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 307     bool has_vga;
 308
 309     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 310     uint8_t irq_state;
 311
 312     /* Capability bits */
 313     uint32_t cap_present;
 314
 315     /* Offset of MSI-X capability in config space */
 316     uint8_t msix_cap;
 317
 318     /* MSI-X entries */
 319     int msix_entries_nr;
 320
 321     /* Space to store MSIX table & pending bit array */
 322     uint8_t *msix_table;
 323     uint8_t *msix_pba;
 324     /* MemoryRegion container for msix exclusive BAR setup */
 325     MemoryRegion msix_exclusive_bar;
 326     /* Memory Regions for MSIX table and pending bit entries. */
 327     MemoryRegion msix_table_mmio;
 328     MemoryRegion msix_pba_mmio;
 329     /* Reference-count for entries actually in use by driver. */
 330     unsigned *msix_entry_used;
 331     /* MSIX function mask set or MSIX disabled */
 332     bool msix_function_masked;
 333     /* Version id needed for VMState */
 334     int32_t version_id;
 335
 336     /* Offset of MSI capability in config space */
 337     uint8_t msi_cap;
 338
 339     /* PCI Express */
 340     PCIExpressDevice exp;
 341
 342     /* SHPC */
 343     SHPCDevice *shpc;
 344
 345     /* Location of option rom */
 346     char *romfile;
 347     bool has_rom;
 348     MemoryRegion rom;
 349     uint32_t rom_bar;
 350
 351     /* INTx routing notifier */
 352     PCIINTxRoutingNotifier intx_routing_notifier;
 353
 354     /* MSI-X notifiers */
 355     MSIVectorUseNotifier msix_vector_use_notifier;
 356     MSIVectorReleaseNotifier msix_vector_release_notifier;
 357     MSIVectorPollNotifier msix_vector_poll_notifier;
 358 };
 359
 360 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 361                       uint8_t attr, MemoryRegion *memory);
 362 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 363                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 364 void pci_unregister_vga(PCIDevice *pci_dev);
 365 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 366
 367 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 368                        uint8_t offset, uint8_t size,
 369                        Error **errp);
 370
 371 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 372
 373 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 374
 375
 376 uint32_t pci_default_read_config(PCIDevice *d,
 377                                  uint32_t address, int len);
 378 void pci_default_write_config(PCIDevice *d,
 379                               uint32_t address, uint32_t val, int len);
 380 void pci_device_save(PCIDevice *s, QEMUFile *f);
 381 int pci_device_load(PCIDevice *s, QEMUFile *f);
 382 MemoryRegion *pci_address_space(PCIDevice *dev);
 383 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 384
 385 /*
 386  * Should not normally be used by devices. For use by sPAPR target
 387  * where QEMU emulates firmware.
 388  */
 389 int pci_bar(PCIDevice *d, int reg);
 390
 391 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 392 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 393 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 394
 395 #define TYPE_PCI_BUS "PCI"
 396 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
 397 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
 398 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
 399 #define TYPE_PCIE_BUS "PCIE"
 400
 401 bool pci_bus_is_express(PCIBus *bus);
 402 bool pci_bus_is_root(PCIBus *bus);
 403 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
 404                          const char *name,
 405                          MemoryRegion *address_space_mem,
 406                          MemoryRegion *address_space_io,
 407                          uint8_t devfn_min, const char *typename);
 408 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 409                     MemoryRegion *address_space_mem,
 410                     MemoryRegion *address_space_io,
 411                     uint8_t devfn_min, const char *typename);
 412 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 413                   void *irq_opaque, int nirq);
 414 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 415 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 416 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 417 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 418                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 419                          void *irq_opaque,
 420                          MemoryRegion *address_space_mem,
 421                          MemoryRegion *address_space_io,
 422                          uint8_t devfn_min, int nirq, const char *typename);
 423 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 424 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 425 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 426 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 427 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 428                                           PCIINTxRoutingNotifier notifier);
 429 void pci_device_reset(PCIDevice *dev);
 430
 431 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
 432                                const char *default_model,
 433                                const char *default_devaddr);
 434
 435 PCIDevice *pci_vga_init(PCIBus *bus);
 436
 437 int pci_bus_num(PCIBus *s);
 438 int pci_bus_numa_node(PCIBus *bus);
 439 void pci_for_each_device(PCIBus *bus, int bus_num,
 440                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 441                          void *opaque);
 442 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
 443                                  void (*fn)(PCIBus *bus, PCIDevice *d,
 444                                             void *opaque),
 445                                  void *opaque);
 446 void pci_for_each_bus_depth_first(PCIBus *bus,
 447                                   void *(*begin)(PCIBus *bus, void *parent_state),
 448                                   void (*end)(PCIBus *bus, void *state),
 449                                   void *parent_state);
 450 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
 451
 452 /* Use this wrapper when specific scan order is not required. */
 453 static inline
 454 void pci_for_each_bus(PCIBus *bus,
 455                       void (*fn)(PCIBus *bus, void *opaque),
 456                       void *opaque)
 457 {
 458     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
 459 }
 460
 461 PCIBus *pci_find_primary_bus(void);
 462 PCIBus *pci_device_root_bus(const PCIDevice *d);
 463 const char *pci_root_bus_path(PCIDevice *dev);
 464 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 465 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 466 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
 467
 468 void pci_device_deassert_intx(PCIDevice *dev);
 469
 470 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
 471
 472 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
 473 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
 474
 475 static inline void
 476 pci_set_byte(uint8_t *config, uint8_t val)
 477 {
 478     *config = val;
 479 }
 480
 481 static inline uint8_t
 482 pci_get_byte(const uint8_t *config)
 483 {
 484     return *config;
 485 }
 486
 487 static inline void
 488 pci_set_word(uint8_t *config, uint16_t val)
 489 {
 490     stw_le_p(config, val);
 491 }
 492
 493 static inline uint16_t
 494 pci_get_word(const uint8_t *config)
 495 {
 496     return lduw_le_p(config);
 497 }
 498
 499 static inline void
 500 pci_set_long(uint8_t *config, uint32_t val)
 501 {
 502     stl_le_p(config, val);
 503 }
 504
 505 static inline uint32_t
 506 pci_get_long(const uint8_t *config)
 507 {
 508     return ldl_le_p(config);
 509 }
 510
 511 /*
 512  * PCI capabilities and/or their fields
 513  * are generally DWORD aligned only so
 514  * mechanism used by pci_set/get_quad()
 515  * must be tolerant to unaligned pointers
 516  *
 517  */
 518 static inline void
 519 pci_set_quad(uint8_t *config, uint64_t val)
 520 {
 521     stq_le_p(config, val);
 522 }
 523
 524 static inline uint64_t
 525 pci_get_quad(const uint8_t *config)
 526 {
 527     return ldq_le_p(config);
 528 }
 529
 530 static inline void
 531 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 532 {
 533     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 534 }
 535
 536 static inline void
 537 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 538 {
 539     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 540 }
 541
 542 static inline void
 543 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 544 {
 545     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 546 }
 547
 548 static inline void
 549 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 550 {
 551     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 552 }
 553
 554 static inline void
 555 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 556 {
 557     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 558 }
 559
 560 static inline void
 561 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 562 {
 563     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 564 }
 565
 566 /*
 567  * helper functions to do bit mask operation on configuration space.
 568  * Just to set bit, use test-and-set and discard returned value.
 569  * Just to clear bit, use test-and-clear and discard returned value.
 570  * NOTE: They aren't atomic.
 571  */
 572 static inline uint8_t
 573 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 574 {
 575     uint8_t val = pci_get_byte(config);
 576     pci_set_byte(config, val & ~mask);
 577     return val & mask;
 578 }
 579
 580 static inline uint8_t
 581 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 582 {
 583     uint8_t val = pci_get_byte(config);
 584     pci_set_byte(config, val | mask);
 585     return val & mask;
 586 }
 587
 588 static inline uint16_t
 589 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 590 {
 591     uint16_t val = pci_get_word(config);
 592     pci_set_word(config, val & ~mask);
 593     return val & mask;
 594 }
 595
 596 static inline uint16_t
 597 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 598 {
 599     uint16_t val = pci_get_word(config);
 600     pci_set_word(config, val | mask);
 601     return val & mask;
 602 }
 603
 604 static inline uint32_t
 605 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 606 {
 607     uint32_t val = pci_get_long(config);
 608     pci_set_long(config, val & ~mask);
 609     return val & mask;
 610 }
 611
 612 static inline uint32_t
 613 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 614 {
 615     uint32_t val = pci_get_long(config);
 616     pci_set_long(config, val | mask);
 617     return val & mask;
 618 }
 619
 620 static inline uint64_t
 621 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 622 {
 623     uint64_t val = pci_get_quad(config);
 624     pci_set_quad(config, val & ~mask);
 625     return val & mask;
 626 }
 627
 628 static inline uint64_t
 629 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 630 {
 631     uint64_t val = pci_get_quad(config);
 632     pci_set_quad(config, val | mask);
 633     return val & mask;
 634 }
 635
 636 /* Access a register specified by a mask */
 637 static inline void
 638 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 639 {
 640     uint8_t val = pci_get_byte(config);
 641     uint8_t rval = reg << ctz32(mask);
 642     pci_set_byte(config, (~mask & val) | (mask & rval));
 643 }
 644
 645 static inline uint8_t
 646 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 647 {
 648     uint8_t val = pci_get_byte(config);
 649     return (val & mask) >> ctz32(mask);
 650 }
 651
 652 static inline void
 653 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 654 {
 655     uint16_t val = pci_get_word(config);
 656     uint16_t rval = reg << ctz32(mask);
 657     pci_set_word(config, (~mask & val) | (mask & rval));
 658 }
 659
 660 static inline uint16_t
 661 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 662 {
 663     uint16_t val = pci_get_word(config);
 664     return (val & mask) >> ctz32(mask);
 665 }
 666
 667 static inline void
 668 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 669 {
 670     uint32_t val = pci_get_long(config);
 671     uint32_t rval = reg << ctz32(mask);
 672     pci_set_long(config, (~mask & val) | (mask & rval));
 673 }
 674
 675 static inline uint32_t
 676 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 677 {
 678     uint32_t val = pci_get_long(config);
 679     return (val & mask) >> ctz32(mask);
 680 }
 681
 682 static inline void
 683 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 684 {
 685     uint64_t val = pci_get_quad(config);
 686     uint64_t rval = reg << ctz32(mask);
 687     pci_set_quad(config, (~mask & val) | (mask & rval));
 688 }
 689
 690 static inline uint64_t
 691 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 692 {
 693     uint64_t val = pci_get_quad(config);
 694     return (val & mask) >> ctz32(mask);
 695 }
 696
 697 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 698                                     const char *name);
 699 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 700                                            bool multifunction,
 701                                            const char *name);
 702 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 703 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 704
 705 void lsi53c895a_create(PCIBus *bus);
 706
 707 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
 708 void pci_set_irq(PCIDevice *pci_dev, int level);
 709
 710 static inline void pci_irq_assert(PCIDevice *pci_dev)
 711 {
 712     pci_set_irq(pci_dev, 1);
 713 }
 714
 715 static inline void pci_irq_deassert(PCIDevice *pci_dev)
 716 {
 717     pci_set_irq(pci_dev, 0);
 718 }
 719
 720 /*
 721  * FIXME: PCI does not work this way.
 722  * All the callers to this method should be fixed.
 723  */
 724 static inline void pci_irq_pulse(PCIDevice *pci_dev)
 725 {
 726     pci_irq_assert(pci_dev);
 727     pci_irq_deassert(pci_dev);
 728 }
 729
 730 static inline int pci_is_express(const PCIDevice *d)
 731 {
 732     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 733 }
 734
 735 static inline uint32_t pci_config_size(const PCIDevice *d)
 736 {
 737     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 738 }
 739
 740 static inline uint16_t pci_get_bdf(PCIDevice *dev)
 741 {
 742     return PCI_BUILD_BDF(pci_bus_num(dev->bus), dev->devfn);
 743 }
 744
 745 uint16_t pci_requester_id(PCIDevice *dev);
 746
 747 /* DMA access functions */
 748 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
 749 {
 750     return &dev->bus_master_as;
 751 }
 752
 753 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 754                              void *buf, dma_addr_t len, DMADirection dir)
 755 {
 756     dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
 757     return 0;
 758 }
 759
 760 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 761                                void *buf, dma_addr_t len)
 762 {
 763     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 764 }
 765
 766 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 767                                 const void *buf, dma_addr_t len)
 768 {
 769     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 770 }
 771
 772 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 773     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 774                                                    dma_addr_t addr)     \
 775     {                                                                   \
 776         return ld##_l##_dma(pci_get_address_space(dev), addr);          \
 777     }                                                                   \
 778     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 779                                         dma_addr_t addr, uint##_bits##_t val) \
 780     {                                                                   \
 781         st##_s##_dma(pci_get_address_space(dev), addr, val);            \
 782     }
 783
 784 PCI_DMA_DEFINE_LDST(ub, b, 8);
 785 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 786 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 787 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 788 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 789 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 790 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 791
 792 #undef PCI_DMA_DEFINE_LDST
 793
 794 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 795                                 dma_addr_t *plen, DMADirection dir)
 796 {
 797     void *buf;
 798
 799     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
 800     return buf;
 801 }
 802
 803 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 804                                  DMADirection dir, dma_addr_t access_len)
 805 {
 806     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
 807 }
 808
 809 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 810                                        int alloc_hint)
 811 {
 812     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
 813 }
 814
 815 extern const VMStateDescription vmstate_pci_device;
 816
 817 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 818     .name       = (stringify(_field)),                               \
 819     .size       = sizeof(PCIDevice),                                 \
 820     .vmsd       = &vmstate_pci_device,                               \
 821     .flags      = VMS_STRUCT,                                        \
 822     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 823 }
 824
 825 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 826     .name       = (stringify(_field)),                               \
 827     .size       = sizeof(PCIDevice),                                 \
 828     .vmsd       = &vmstate_pci_device,                               \
 829     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 830     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 831 }
 832
 833 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
 834
 835 #endif