| commit | e35310260ec57d20301c65a5714ca55369e971cc | |
| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | |
| Fri, 15 May 2015 02:22:55 +0000 (14 19:22 -0700) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 18 May 2015 15:41:08 +0000 (18 16:41 +0100) | ||
| tree | 823e928135fa03a39d030cdc26dc0124e6be0032 | treesnapshot (tar.gz zip) |
| parent | ee804264ddc4d3cd36a5183a09847e391da0fc66 | commitdiff |
target-arm: cpu64: Add support for Cortex-A53
Add the ARM Cortex-A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: db439ff834cf0431bc192b05272a3b28fe2045d0.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add the ARM Cortex-A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: db439ff834cf0431bc192b05272a3b28fe2045d0.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target-arm/cpu64.c | diffblobblamehistory |