3 #include "sysemu/kvm.h"
4 #include "helper_regs.h"
6 static int cpu_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
8 PowerPCCPU
*cpu
= opaque
;
9 CPUPPCState
*env
= &cpu
->env
;
15 for (i
= 0; i
< 32; i
++)
16 qemu_get_betls(f
, &env
->gpr
[i
]);
17 #if !defined(TARGET_PPC64)
18 for (i
= 0; i
< 32; i
++)
19 qemu_get_betls(f
, &env
->gprh
[i
]);
21 qemu_get_betls(f
, &env
->lr
);
22 qemu_get_betls(f
, &env
->ctr
);
23 for (i
= 0; i
< 8; i
++)
24 qemu_get_be32s(f
, &env
->crf
[i
]);
25 qemu_get_betls(f
, &xer
);
26 cpu_write_xer(env
, xer
);
27 qemu_get_betls(f
, &env
->reserve_addr
);
28 qemu_get_betls(f
, &env
->msr
);
29 for (i
= 0; i
< 4; i
++)
30 qemu_get_betls(f
, &env
->tgpr
[i
]);
31 for (i
= 0; i
< 32; i
++) {
36 u
.l
= qemu_get_be64(f
);
39 qemu_get_be32s(f
, &fpscr
);
41 qemu_get_sbe32s(f
, &env
->access_type
);
42 #if defined(TARGET_PPC64)
43 qemu_get_betls(f
, &env
->spr
[SPR_ASR
]);
44 qemu_get_sbe32s(f
, &env
->slb_nr
);
46 qemu_get_betls(f
, &sdr1
);
47 for (i
= 0; i
< 32; i
++)
48 qemu_get_betls(f
, &env
->sr
[i
]);
49 for (i
= 0; i
< 2; i
++)
50 for (j
= 0; j
< 8; j
++)
51 qemu_get_betls(f
, &env
->DBAT
[i
][j
]);
52 for (i
= 0; i
< 2; i
++)
53 for (j
= 0; j
< 8; j
++)
54 qemu_get_betls(f
, &env
->IBAT
[i
][j
]);
55 qemu_get_sbe32s(f
, &env
->nb_tlb
);
56 qemu_get_sbe32s(f
, &env
->tlb_per_way
);
57 qemu_get_sbe32s(f
, &env
->nb_ways
);
58 qemu_get_sbe32s(f
, &env
->last_way
);
59 qemu_get_sbe32s(f
, &env
->id_tlbs
);
60 qemu_get_sbe32s(f
, &env
->nb_pids
);
63 for (i
= 0; i
< env
->nb_tlb
; i
++) {
64 qemu_get_betls(f
, &env
->tlb
.tlb6
[i
].pte0
);
65 qemu_get_betls(f
, &env
->tlb
.tlb6
[i
].pte1
);
66 qemu_get_betls(f
, &env
->tlb
.tlb6
[i
].EPN
);
69 for (i
= 0; i
< 4; i
++)
70 qemu_get_betls(f
, &env
->pb
[i
]);
71 for (i
= 0; i
< 1024; i
++)
72 qemu_get_betls(f
, &env
->spr
[i
]);
73 if (!env
->external_htab
) {
74 ppc_store_sdr1(env
, sdr1
);
76 qemu_get_be32s(f
, &env
->vscr
);
77 qemu_get_be64s(f
, &env
->spe_acc
);
78 qemu_get_be32s(f
, &env
->spe_fscr
);
79 qemu_get_betls(f
, &env
->msr_mask
);
80 qemu_get_be32s(f
, &env
->flags
);
81 qemu_get_sbe32s(f
, &env
->error_code
);
82 qemu_get_be32s(f
, &env
->pending_interrupts
);
83 qemu_get_be32s(f
, &env
->irq_input_state
);
84 for (i
= 0; i
< POWERPC_EXCP_NB
; i
++)
85 qemu_get_betls(f
, &env
->excp_vectors
[i
]);
86 qemu_get_betls(f
, &env
->excp_prefix
);
87 qemu_get_betls(f
, &env
->ivor_mask
);
88 qemu_get_betls(f
, &env
->ivpr_mask
);
89 qemu_get_betls(f
, &env
->hreset_vector
);
90 qemu_get_betls(f
, &env
->nip
);
91 qemu_get_betls(f
, &env
->hflags
);
92 qemu_get_betls(f
, &env
->hflags_nmsr
);
93 qemu_get_sbe32s(f
, &env
->mmu_idx
);
94 qemu_get_sbe32(f
); /* Discard unused power_mode */
99 static int get_avr(QEMUFile
*f
, void *pv
, size_t size
)
103 v
->u64
[0] = qemu_get_be64(f
);
104 v
->u64
[1] = qemu_get_be64(f
);
109 static void put_avr(QEMUFile
*f
, void *pv
, size_t size
)
113 qemu_put_be64(f
, v
->u64
[0]);
114 qemu_put_be64(f
, v
->u64
[1]);
117 static const VMStateInfo vmstate_info_avr
= {
123 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
124 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
126 #define VMSTATE_AVR_ARRAY(_f, _s, _n) \
127 VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
129 static void cpu_pre_save(void *opaque
)
131 PowerPCCPU
*cpu
= opaque
;
132 CPUPPCState
*env
= &cpu
->env
;
135 env
->spr
[SPR_LR
] = env
->lr
;
136 env
->spr
[SPR_CTR
] = env
->ctr
;
137 env
->spr
[SPR_XER
] = env
->xer
;
138 #if defined(TARGET_PPC64)
139 env
->spr
[SPR_CFAR
] = env
->cfar
;
141 env
->spr
[SPR_BOOKE_SPEFSCR
] = env
->spe_fscr
;
143 for (i
= 0; (i
< 4) && (i
< env
->nb_BATs
); i
++) {
144 env
->spr
[SPR_DBAT0U
+ 2*i
] = env
->DBAT
[0][i
];
145 env
->spr
[SPR_DBAT0U
+ 2*i
+ 1] = env
->DBAT
[1][i
];
146 env
->spr
[SPR_IBAT0U
+ 2*i
] = env
->IBAT
[0][i
];
147 env
->spr
[SPR_IBAT0U
+ 2*i
+ 1] = env
->IBAT
[1][i
];
149 for (i
= 0; (i
< 4) && ((i
+4) < env
->nb_BATs
); i
++) {
150 env
->spr
[SPR_DBAT4U
+ 2*i
] = env
->DBAT
[0][i
+4];
151 env
->spr
[SPR_DBAT4U
+ 2*i
+ 1] = env
->DBAT
[1][i
+4];
152 env
->spr
[SPR_IBAT4U
+ 2*i
] = env
->IBAT
[0][i
+4];
153 env
->spr
[SPR_IBAT4U
+ 2*i
+ 1] = env
->IBAT
[1][i
+4];
157 static int cpu_post_load(void *opaque
, int version_id
)
159 PowerPCCPU
*cpu
= opaque
;
160 CPUPPCState
*env
= &cpu
->env
;
163 env
->lr
= env
->spr
[SPR_LR
];
164 env
->ctr
= env
->spr
[SPR_CTR
];
165 env
->xer
= env
->spr
[SPR_XER
];
166 #if defined(TARGET_PPC64)
167 env
->cfar
= env
->spr
[SPR_CFAR
];
169 env
->spe_fscr
= env
->spr
[SPR_BOOKE_SPEFSCR
];
171 for (i
= 0; (i
< 4) && (i
< env
->nb_BATs
); i
++) {
172 env
->DBAT
[0][i
] = env
->spr
[SPR_DBAT0U
+ 2*i
];
173 env
->DBAT
[1][i
] = env
->spr
[SPR_DBAT0U
+ 2*i
+ 1];
174 env
->IBAT
[0][i
] = env
->spr
[SPR_IBAT0U
+ 2*i
];
175 env
->IBAT
[1][i
] = env
->spr
[SPR_IBAT0U
+ 2*i
+ 1];
177 for (i
= 0; (i
< 4) && ((i
+4) < env
->nb_BATs
); i
++) {
178 env
->DBAT
[0][i
+4] = env
->spr
[SPR_DBAT4U
+ 2*i
];
179 env
->DBAT
[1][i
+4] = env
->spr
[SPR_DBAT4U
+ 2*i
+ 1];
180 env
->IBAT
[0][i
+4] = env
->spr
[SPR_IBAT4U
+ 2*i
];
181 env
->IBAT
[1][i
+4] = env
->spr
[SPR_IBAT4U
+ 2*i
+ 1];
184 if (!env
->external_htab
) {
185 /* Restore htab_base and htab_mask variables */
186 ppc_store_sdr1(env
, env
->spr
[SPR_SDR1
]);
188 hreg_compute_hflags(env
);
189 hreg_compute_mem_idx(env
);
194 static bool fpu_needed(void *opaque
)
196 PowerPCCPU
*cpu
= opaque
;
198 return (cpu
->env
.insns_flags
& PPC_FLOAT
);
201 static const VMStateDescription vmstate_fpu
= {
204 .minimum_version_id
= 1,
205 .fields
= (VMStateField
[]) {
206 VMSTATE_FLOAT64_ARRAY(env
.fpr
, PowerPCCPU
, 32),
207 VMSTATE_UINTTL(env
.fpscr
, PowerPCCPU
),
208 VMSTATE_END_OF_LIST()
212 static bool altivec_needed(void *opaque
)
214 PowerPCCPU
*cpu
= opaque
;
216 return (cpu
->env
.insns_flags
& PPC_ALTIVEC
);
219 static const VMStateDescription vmstate_altivec
= {
220 .name
= "cpu/altivec",
222 .minimum_version_id
= 1,
223 .fields
= (VMStateField
[]) {
224 VMSTATE_AVR_ARRAY(env
.avr
, PowerPCCPU
, 32),
225 VMSTATE_UINT32(env
.vscr
, PowerPCCPU
),
226 VMSTATE_END_OF_LIST()
230 static bool vsx_needed(void *opaque
)
232 PowerPCCPU
*cpu
= opaque
;
234 return (cpu
->env
.insns_flags2
& PPC2_VSX
);
237 static const VMStateDescription vmstate_vsx
= {
240 .minimum_version_id
= 1,
241 .fields
= (VMStateField
[]) {
242 VMSTATE_UINT64_ARRAY(env
.vsr
, PowerPCCPU
, 32),
243 VMSTATE_END_OF_LIST()
247 static bool sr_needed(void *opaque
)
250 PowerPCCPU
*cpu
= opaque
;
252 return !(cpu
->env
.mmu_model
& POWERPC_MMU_64
);
258 static const VMStateDescription vmstate_sr
= {
261 .minimum_version_id
= 1,
262 .fields
= (VMStateField
[]) {
263 VMSTATE_UINTTL_ARRAY(env
.sr
, PowerPCCPU
, 32),
264 VMSTATE_END_OF_LIST()
269 static int get_slbe(QEMUFile
*f
, void *pv
, size_t size
)
273 v
->esid
= qemu_get_be64(f
);
274 v
->vsid
= qemu_get_be64(f
);
279 static void put_slbe(QEMUFile
*f
, void *pv
, size_t size
)
283 qemu_put_be64(f
, v
->esid
);
284 qemu_put_be64(f
, v
->vsid
);
287 static const VMStateInfo vmstate_info_slbe
= {
293 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
294 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
296 #define VMSTATE_SLB_ARRAY(_f, _s, _n) \
297 VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
299 static bool slb_needed(void *opaque
)
301 PowerPCCPU
*cpu
= opaque
;
303 /* We don't support any of the old segment table based 64-bit CPUs */
304 return (cpu
->env
.mmu_model
& POWERPC_MMU_64
);
307 static const VMStateDescription vmstate_slb
= {
310 .minimum_version_id
= 1,
311 .fields
= (VMStateField
[]) {
312 VMSTATE_INT32_EQUAL(env
.slb_nr
, PowerPCCPU
),
313 VMSTATE_SLB_ARRAY(env
.slb
, PowerPCCPU
, MAX_SLB_ENTRIES
),
314 VMSTATE_END_OF_LIST()
317 #endif /* TARGET_PPC64 */
319 static const VMStateDescription vmstate_tlb6xx_entry
= {
320 .name
= "cpu/tlb6xx_entry",
322 .minimum_version_id
= 1,
323 .fields
= (VMStateField
[]) {
324 VMSTATE_UINTTL(pte0
, ppc6xx_tlb_t
),
325 VMSTATE_UINTTL(pte1
, ppc6xx_tlb_t
),
326 VMSTATE_UINTTL(EPN
, ppc6xx_tlb_t
),
327 VMSTATE_END_OF_LIST()
331 static bool tlb6xx_needed(void *opaque
)
333 PowerPCCPU
*cpu
= opaque
;
334 CPUPPCState
*env
= &cpu
->env
;
336 return env
->nb_tlb
&& (env
->tlb_type
== TLB_6XX
);
339 static const VMStateDescription vmstate_tlb6xx
= {
340 .name
= "cpu/tlb6xx",
342 .minimum_version_id
= 1,
343 .fields
= (VMStateField
[]) {
344 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
),
345 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlb6
, PowerPCCPU
,
347 vmstate_tlb6xx_entry
,
349 VMSTATE_UINTTL_ARRAY(env
.tgpr
, PowerPCCPU
, 4),
350 VMSTATE_END_OF_LIST()
354 static const VMStateDescription vmstate_tlbemb_entry
= {
355 .name
= "cpu/tlbemb_entry",
357 .minimum_version_id
= 1,
358 .fields
= (VMStateField
[]) {
359 VMSTATE_UINT64(RPN
, ppcemb_tlb_t
),
360 VMSTATE_UINTTL(EPN
, ppcemb_tlb_t
),
361 VMSTATE_UINTTL(PID
, ppcemb_tlb_t
),
362 VMSTATE_UINTTL(size
, ppcemb_tlb_t
),
363 VMSTATE_UINT32(prot
, ppcemb_tlb_t
),
364 VMSTATE_UINT32(attr
, ppcemb_tlb_t
),
365 VMSTATE_END_OF_LIST()
369 static bool tlbemb_needed(void *opaque
)
371 PowerPCCPU
*cpu
= opaque
;
372 CPUPPCState
*env
= &cpu
->env
;
374 return env
->nb_tlb
&& (env
->tlb_type
== TLB_EMB
);
377 static bool pbr403_needed(void *opaque
)
379 PowerPCCPU
*cpu
= opaque
;
380 uint32_t pvr
= cpu
->env
.spr
[SPR_PVR
];
382 return (pvr
& 0xffff0000) == 0x00200000;
385 static const VMStateDescription vmstate_pbr403
= {
386 .name
= "cpu/pbr403",
388 .minimum_version_id
= 1,
389 .fields
= (VMStateField
[]) {
390 VMSTATE_UINTTL_ARRAY(env
.pb
, PowerPCCPU
, 4),
391 VMSTATE_END_OF_LIST()
395 static const VMStateDescription vmstate_tlbemb
= {
396 .name
= "cpu/tlb6xx",
398 .minimum_version_id
= 1,
399 .fields
= (VMStateField
[]) {
400 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
),
401 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlbe
, PowerPCCPU
,
403 vmstate_tlbemb_entry
,
405 /* 403 protection registers */
406 VMSTATE_END_OF_LIST()
408 .subsections
= (VMStateSubsection
[]) {
410 .vmsd
= &vmstate_pbr403
,
411 .needed
= pbr403_needed
,
418 static const VMStateDescription vmstate_tlbmas_entry
= {
419 .name
= "cpu/tlbmas_entry",
421 .minimum_version_id
= 1,
422 .fields
= (VMStateField
[]) {
423 VMSTATE_UINT32(mas8
, ppcmas_tlb_t
),
424 VMSTATE_UINT32(mas1
, ppcmas_tlb_t
),
425 VMSTATE_UINT64(mas2
, ppcmas_tlb_t
),
426 VMSTATE_UINT64(mas7_3
, ppcmas_tlb_t
),
427 VMSTATE_END_OF_LIST()
431 static bool tlbmas_needed(void *opaque
)
433 PowerPCCPU
*cpu
= opaque
;
434 CPUPPCState
*env
= &cpu
->env
;
436 return env
->nb_tlb
&& (env
->tlb_type
== TLB_MAS
);
439 static const VMStateDescription vmstate_tlbmas
= {
440 .name
= "cpu/tlbmas",
442 .minimum_version_id
= 1,
443 .fields
= (VMStateField
[]) {
444 VMSTATE_INT32_EQUAL(env
.nb_tlb
, PowerPCCPU
),
445 VMSTATE_STRUCT_VARRAY_POINTER_INT32(env
.tlb
.tlbm
, PowerPCCPU
,
447 vmstate_tlbmas_entry
,
449 VMSTATE_END_OF_LIST()
453 const VMStateDescription vmstate_ppc_cpu
= {
456 .minimum_version_id
= 5,
457 .minimum_version_id_old
= 4,
458 .load_state_old
= cpu_load_old
,
459 .pre_save
= cpu_pre_save
,
460 .post_load
= cpu_post_load
,
461 .fields
= (VMStateField
[]) {
462 /* Verify we haven't changed the pvr */
463 VMSTATE_UINTTL_EQUAL(env
.spr
[SPR_PVR
], PowerPCCPU
),
465 /* User mode architected state */
466 VMSTATE_UINTTL_ARRAY(env
.gpr
, PowerPCCPU
, 32),
467 #if !defined(TARGET_PPC64)
468 VMSTATE_UINTTL_ARRAY(env
.gprh
, PowerPCCPU
, 32),
470 VMSTATE_UINT32_ARRAY(env
.crf
, PowerPCCPU
, 8),
471 VMSTATE_UINTTL(env
.nip
, PowerPCCPU
),
474 VMSTATE_UINTTL_ARRAY(env
.spr
, PowerPCCPU
, 1024),
475 VMSTATE_UINT64(env
.spe_acc
, PowerPCCPU
),
478 VMSTATE_UINTTL(env
.reserve_addr
, PowerPCCPU
),
480 /* Supervisor mode architected state */
481 VMSTATE_UINTTL(env
.msr
, PowerPCCPU
),
484 VMSTATE_UINTTL(env
.hflags_nmsr
, PowerPCCPU
),
485 /* FIXME: access_type? */
487 /* Sanity checking */
488 VMSTATE_UINTTL_EQUAL(env
.msr_mask
, PowerPCCPU
),
489 VMSTATE_UINT64_EQUAL(env
.insns_flags
, PowerPCCPU
),
490 VMSTATE_UINT64_EQUAL(env
.insns_flags2
, PowerPCCPU
),
491 VMSTATE_UINT32_EQUAL(env
.nb_BATs
, PowerPCCPU
),
492 VMSTATE_END_OF_LIST()
494 .subsections
= (VMStateSubsection
[]) {
496 .vmsd
= &vmstate_fpu
,
497 .needed
= fpu_needed
,
499 .vmsd
= &vmstate_altivec
,
500 .needed
= altivec_needed
,
502 .vmsd
= &vmstate_vsx
,
503 .needed
= vsx_needed
,
509 .vmsd
= &vmstate_slb
,
510 .needed
= slb_needed
,
512 #endif /* TARGET_PPC64 */
513 .vmsd
= &vmstate_tlb6xx
,
514 .needed
= tlb6xx_needed
,
516 .vmsd
= &vmstate_tlbemb
,
517 .needed
= tlbemb_needed
,
519 .vmsd
= &vmstate_tlbmas
,
520 .needed
= tlbmas_needed
,