2 * IMX31 Clock Control Module
4 * Copyright (C) 2012 NICTA
5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
10 * To get the timer frequencies right, we need to emulate at least part of
14 #include "qemu/osdep.h"
15 #include "hw/misc/imx31_ccm.h"
17 #define CKIH_FREQ 26000000 /* 26MHz crystal input */
19 #ifndef DEBUG_IMX31_CCM
20 #define DEBUG_IMX31_CCM 0
23 #define DPRINTF(fmt, args...) \
25 if (DEBUG_IMX31_CCM) { \
26 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
31 static char const *imx31_ccm_reg_name(uint32_t reg
)
33 static char unknown
[20];
36 case IMX31_CCM_CCMR_REG
:
38 case IMX31_CCM_PDR0_REG
:
40 case IMX31_CCM_PDR1_REG
:
42 case IMX31_CCM_RCSR_REG
:
44 case IMX31_CCM_MPCTL_REG
:
46 case IMX31_CCM_UPCTL_REG
:
48 case IMX31_CCM_SPCTL_REG
:
50 case IMX31_CCM_COSR_REG
:
52 case IMX31_CCM_CGR0_REG
:
54 case IMX31_CCM_CGR1_REG
:
56 case IMX31_CCM_CGR2_REG
:
58 case IMX31_CCM_WIMR_REG
:
60 case IMX31_CCM_LDC_REG
:
62 case IMX31_CCM_DCVR0_REG
:
64 case IMX31_CCM_DCVR1_REG
:
66 case IMX31_CCM_DCVR2_REG
:
68 case IMX31_CCM_DCVR3_REG
:
70 case IMX31_CCM_LTR0_REG
:
72 case IMX31_CCM_LTR1_REG
:
74 case IMX31_CCM_LTR2_REG
:
76 case IMX31_CCM_LTR3_REG
:
78 case IMX31_CCM_LTBR0_REG
:
80 case IMX31_CCM_LTBR1_REG
:
82 case IMX31_CCM_PMCR0_REG
:
84 case IMX31_CCM_PMCR1_REG
:
86 case IMX31_CCM_PDR2_REG
:
89 sprintf(unknown
, "[%d ?]", reg
);
94 static const VMStateDescription vmstate_imx31_ccm
= {
95 .name
= TYPE_IMX31_CCM
,
97 .minimum_version_id
= 2,
98 .fields
= (VMStateField
[]) {
99 VMSTATE_UINT32_ARRAY(reg
, IMX31CCMState
, IMX31_CCM_MAX_REG
),
100 VMSTATE_END_OF_LIST()
104 static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState
*dev
)
107 IMX31CCMState
*s
= IMX31_CCM(dev
);
109 if ((s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_PRCS
) == 2) {
110 if (s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_FPME
) {
112 if (s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_FPMF
) {
120 DPRINTF("freq = %d\n", freq
);
125 static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState
*dev
)
128 IMX31CCMState
*s
= IMX31_CCM(dev
);
130 freq
= imx_ccm_calc_pll(s
->reg
[IMX31_CCM_MPCTL_REG
],
131 imx31_ccm_get_pll_ref_clk(dev
));
133 DPRINTF("freq = %d\n", freq
);
138 static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState
*dev
)
141 IMX31CCMState
*s
= IMX31_CCM(dev
);
143 if ((s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_MDS
) ||
144 !(s
->reg
[IMX31_CCM_CCMR_REG
] & CCMR_MPE
)) {
145 freq
= imx31_ccm_get_pll_ref_clk(dev
);
147 freq
= imx31_ccm_get_mpll_clk(dev
);
150 DPRINTF("freq = %d\n", freq
);
155 static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState
*dev
)
158 IMX31CCMState
*s
= IMX31_CCM(dev
);
160 freq
= imx31_ccm_get_mcu_main_clk(dev
)
161 / (1 + EXTRACT(s
->reg
[IMX31_CCM_PDR0_REG
], MAX
));
163 DPRINTF("freq = %d\n", freq
);
168 static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState
*dev
)
171 IMX31CCMState
*s
= IMX31_CCM(dev
);
173 freq
= imx31_ccm_get_hclk_clk(dev
)
174 / (1 + EXTRACT(s
->reg
[IMX31_CCM_PDR0_REG
], IPG
));
176 DPRINTF("freq = %d\n", freq
);
181 static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState
*dev
, IMXClk clock
)
189 freq
= imx31_ccm_get_ipg_clk(dev
);
195 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: unsupported clock %d\n",
196 TYPE_IMX31_CCM
, __func__
, clock
);
200 DPRINTF("Clock = %d) = %d\n", clock
, freq
);
205 static void imx31_ccm_reset(DeviceState
*dev
)
207 IMX31CCMState
*s
= IMX31_CCM(dev
);
211 memset(s
->reg
, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG
);
213 s
->reg
[IMX31_CCM_CCMR_REG
] = 0x074b0b7d;
214 s
->reg
[IMX31_CCM_PDR0_REG
] = 0xff870b48;
215 s
->reg
[IMX31_CCM_PDR1_REG
] = 0x49fcfe7f;
216 s
->reg
[IMX31_CCM_RCSR_REG
] = 0x007f0000;
217 s
->reg
[IMX31_CCM_MPCTL_REG
] = 0x04001800;
218 s
->reg
[IMX31_CCM_UPCTL_REG
] = 0x04051c03;
219 s
->reg
[IMX31_CCM_SPCTL_REG
] = 0x04043001;
220 s
->reg
[IMX31_CCM_COSR_REG
] = 0x00000280;
221 s
->reg
[IMX31_CCM_CGR0_REG
] = 0xffffffff;
222 s
->reg
[IMX31_CCM_CGR1_REG
] = 0xffffffff;
223 s
->reg
[IMX31_CCM_CGR2_REG
] = 0xffffffff;
224 s
->reg
[IMX31_CCM_WIMR_REG
] = 0xffffffff;
225 s
->reg
[IMX31_CCM_LTR1_REG
] = 0x00004040;
226 s
->reg
[IMX31_CCM_PMCR0_REG
] = 0x80209828;
227 s
->reg
[IMX31_CCM_PMCR1_REG
] = 0x00aa0000;
228 s
->reg
[IMX31_CCM_PDR2_REG
] = 0x00000285;
231 static uint64_t imx31_ccm_read(void *opaque
, hwaddr offset
, unsigned size
)
234 IMX31CCMState
*s
= (IMX31CCMState
*)opaque
;
236 if ((offset
>> 2) < IMX31_CCM_MAX_REG
) {
237 value
= s
->reg
[offset
>> 2];
239 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
240 HWADDR_PRIx
"\n", TYPE_IMX31_CCM
, __func__
, offset
);
243 DPRINTF("reg[%s] => 0x%" PRIx32
"\n", imx31_ccm_reg_name(offset
>> 2),
246 return (uint64_t)value
;
249 static void imx31_ccm_write(void *opaque
, hwaddr offset
, uint64_t value
,
252 IMX31CCMState
*s
= (IMX31CCMState
*)opaque
;
254 DPRINTF("reg[%s] <= 0x%" PRIx32
"\n", imx31_ccm_reg_name(offset
>> 2),
257 switch (offset
>> 2) {
258 case IMX31_CCM_CCMR_REG
:
259 s
->reg
[IMX31_CCM_CCMR_REG
] = CCMR_FPMF
| (value
& 0x3b6fdfff);
261 case IMX31_CCM_PDR0_REG
:
262 s
->reg
[IMX31_CCM_PDR0_REG
] = value
& 0xff9f3fff;
264 case IMX31_CCM_PDR1_REG
:
265 s
->reg
[IMX31_CCM_PDR1_REG
] = value
;
267 case IMX31_CCM_MPCTL_REG
:
268 s
->reg
[IMX31_CCM_MPCTL_REG
] = value
& 0xbfff3fff;
270 case IMX31_CCM_SPCTL_REG
:
271 s
->reg
[IMX31_CCM_SPCTL_REG
] = value
& 0xbfff3fff;
273 case IMX31_CCM_CGR0_REG
:
274 s
->reg
[IMX31_CCM_CGR0_REG
] = value
;
276 case IMX31_CCM_CGR1_REG
:
277 s
->reg
[IMX31_CCM_CGR1_REG
] = value
;
279 case IMX31_CCM_CGR2_REG
:
280 s
->reg
[IMX31_CCM_CGR2_REG
] = value
;
283 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
284 HWADDR_PRIx
"\n", TYPE_IMX31_CCM
, __func__
, offset
);
289 static const struct MemoryRegionOps imx31_ccm_ops
= {
290 .read
= imx31_ccm_read
,
291 .write
= imx31_ccm_write
,
292 .endianness
= DEVICE_NATIVE_ENDIAN
,
295 * Our device would not work correctly if the guest was doing
296 * unaligned access. This might not be a limitation on the real
297 * device but in practice there is no reason for a guest to access
298 * this device unaligned.
300 .min_access_size
= 4,
301 .max_access_size
= 4,
307 static void imx31_ccm_init(Object
*obj
)
309 DeviceState
*dev
= DEVICE(obj
);
310 SysBusDevice
*sd
= SYS_BUS_DEVICE(obj
);
311 IMX31CCMState
*s
= IMX31_CCM(obj
);
313 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &imx31_ccm_ops
, s
,
314 TYPE_IMX31_CCM
, 0x1000);
315 sysbus_init_mmio(sd
, &s
->iomem
);
318 static void imx31_ccm_class_init(ObjectClass
*klass
, void *data
)
320 DeviceClass
*dc
= DEVICE_CLASS(klass
);
321 IMXCCMClass
*ccm
= IMX_CCM_CLASS(klass
);
323 dc
->reset
= imx31_ccm_reset
;
324 dc
->vmsd
= &vmstate_imx31_ccm
;
325 dc
->desc
= "i.MX31 Clock Control Module";
327 ccm
->get_clock_frequency
= imx31_ccm_get_clock_frequency
;
330 static const TypeInfo imx31_ccm_info
= {
331 .name
= TYPE_IMX31_CCM
,
332 .parent
= TYPE_IMX_CCM
,
333 .instance_size
= sizeof(IMX31CCMState
),
334 .instance_init
= imx31_ccm_init
,
335 .class_init
= imx31_ccm_class_init
,
338 static void imx31_ccm_register_types(void)
340 type_register_static(&imx31_ccm_info
);
343 type_init(imx31_ccm_register_types
)